ArmPkg/Drivers/PL390Gic/PL390GicSec.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Uefi.h>
  16 #include <Library/IoLib.h>
  17 #include <Library/ArmGicLib.h>
  18
  19 /*
  20  * This function configures the all interrupts to be Non-secure.
  21  *
  22  */
  23 VOID
  24 EFIAPI
  25 ArmGicSetupNonSecure (
  26   IN  INTN          GicDistributorBase,
  27   IN  INTN          GicInterruptInterfaceBase
  28   )
  29 {
  30   UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
  31
  32   // Set priority Mask so that no interrupts get through to CPU
  33   MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
  34
  35   // Check if there are any pending interrupts
  36   //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
  37   while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
  38     // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
  39     UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
  40
  41     // Write to End of interrupt signal
  42     MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
  43   }
  44
  45   // Ensure all GIC interrupts are Non-Secure
  46   MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
  47   MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
  48   MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
  49
  50   // Ensure all interrupts can get through the priority mask
  51   MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
  52 }
  53
  54 VOID
  55 EFIAPI
  56 ArmGicEnableInterruptInterface (
  57   IN  INTN          GicInterruptInterfaceBase
  58   )
  59 {
  60   MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);  /* Set Priority Mask to allow interrupts */
  61
  62   /*
  63    * Enable CPU interface in Secure world
  64      * Enable CPU inteface in Non-secure World
  65    * Signal Secure Interrupts to CPU using FIQ line *
  66    */
  67   MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
  68       ARM_GIC_ICCICR_ENABLE_SECURE |
  69       ARM_GIC_ICCICR_ENABLE_NS |
  70       ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
  71 }
  72
  73 VOID
  74 EFIAPI
  75 ArmGicEnableDistributor (
  76   IN  INTN          GicDistributorBase
  77   )
  78 {
  79   MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1);               // turn on the GIC distributor
  80 }