ArmPkg/Include/Chipset/ArmV7.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __ARM_V7_H__
  16 #define __ARM_V7_H__
  17
  18 #include <Chipset/ArmV7Mmu.h>
  19
  20 // Domain Access Control Register
  21 #define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))
  22 #define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))
  23 #define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))
  24 #define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
  25 #define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))
  26
  27 // Cortex A9 feature bit definitions
  28 #define A9_FEATURE_PARITY  (1<<9)
  29 #define A9_FEATURE_AOW     (1<<8)
  30 #define A9_FEATURE_EXCL    (1<<7)
  31 #define A9_FEATURE_SMP     (1<<6)
  32 #define A9_FEATURE_FOZ     (1<<3)
  33 #define A9_FEATURE_DPREF   (1<<2)
  34 #define A9_FEATURE_HINT    (1<<1)
  35 #define A9_FEATURE_FWD     (1<<0)
  36
  37 // SCU register offsets & masks
  38 #define SCU_CONTROL_OFFSET       0x0
  39 #define SCU_CONFIG_OFFSET        0x4
  40 #define SCU_INVALL_OFFSET        0xC
  41 #define SCU_FILT_START_OFFSET    0x40
  42 #define SCU_FILT_END_OFFSET      0x44
  43 #define SCU_SACR_OFFSET          0x50
  44 #define SCU_SSACR_OFFSET         0x54
  45
  46 #define SMP_GIC_CPUIF_BASE       0x100
  47 #define SMP_GIC_DIST_BASE        0x1000
  48
  49 // CPACR - Coprocessor Access Control Register definitions
  50 #define CPACR_CP_DENIED(cp)     0x00
  51 #define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
  52 #define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
  53 #define CPACR_ASEDIS            (1 << 31)
  54 #define CPACR_D32DIS            (1 << 30)
  55 #define CPACR_CP_FULL_ACCESS    0x0FFFFFFF
  56
  57 // NSACR - Non-Secure Access Control Register definitions
  58 #define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
  59 #define NSACR_NSD32DIS          (1 << 14)
  60 #define NSACR_NSASEDIS          (1 << 15)
  61 #define NSACR_PLE               (1 << 16)
  62 #define NSACR_TL                (1 << 17)
  63 #define NSACR_NS_SMP            (1 << 18)
  64 #define NSACR_RFR               (1 << 19)
  65
  66 // SCR - Secure Configuration Register definitions
  67 #define SCR_NS                  (1 << 0)
  68 #define SCR_IRQ                 (1 << 1)
  69 #define SCR_FIQ                 (1 << 2)
  70 #define SCR_EA                  (1 << 3)
  71 #define SCR_FW                  (1 << 4)
  72 #define SCR_AW                  (1 << 5)
  73
  74 VOID
  75 EFIAPI
  76 ArmEnableSWPInstruction (
  77   VOID
  78   );
  79
  80 VOID
  81 EFIAPI
  82 ArmWriteNsacr (
  83   IN  UINT32   SetWayFormat
  84   );
  85
  86 VOID
  87 EFIAPI
  88 ArmWriteScr (
  89   IN  UINT32   SetWayFormat
  90   );
  91
  92 VOID
  93 EFIAPI
  94 ArmWriteVMBar (
  95   IN  UINT32   SetWayFormat
  96   );
  97
  98 VOID
  99 EFIAPI
 100 ArmWriteVBar (
 101   IN  UINT32   SetWayFormat
 102   );
 103
 104 UINT32
 105 EFIAPI
 106 ArmReadVBar (
 107   VOID
 108   );
 109
 110 VOID
 111 EFIAPI
 112 ArmWriteCPACR (
 113   IN  UINT32   SetWayFormat
 114   );
 115
 116 VOID
 117 EFIAPI
 118 ArmEnableVFP (
 119   VOID
 120   );
 121
 122 VOID
 123 EFIAPI
 124 ArmCallWFI (
 125   VOID
 126   );
 127
 128 VOID
 129 EFIAPI
 130 ArmInvalidScu (
 131   VOID
 132   );
 133
 134 UINTN
 135 EFIAPI
 136 ArmGetScuBaseAddress (
 137   VOID
 138   );
 139
 140 UINT32
 141 EFIAPI
 142 ArmIsScuEnable (
 143   VOID
 144   );
 145
 146 VOID
 147 EFIAPI
 148 ArmWriteAuxCr (
 149   IN  UINT32    Bit
 150   );
 151
 152 UINT32
 153 EFIAPI
 154 ArmReadAuxCr (
 155   VOID
 156   );
 157
 158 VOID
 159 EFIAPI
 160 ArmSetAuxCrBit (
 161   IN  UINT32    Bits
 162   );
 163
 164 VOID
 165 EFIAPI
 166 ArmSetupSmpNonSecure (
 167   IN  UINTN                     CoreId
 168   );
 169
 170 UINTN
 171 EFIAPI
 172 ArmReadCbar (
 173   VOID
 174   );
 175
 176 VOID
 177 EFIAPI
 178 ArmInvalidateInstructionAndDataTlb (
 179   VOID
 180   );
 181
 182
 183 UINTN
 184 EFIAPI
 185 ArmReadMpidr (
 186   VOID
 187   );
 188
 189 UINTN
 190 EFIAPI
 191 ArmReadTpidrurw (
 192   VOID
 193   );
 194
 195 VOID
 196 EFIAPI
 197 ArmWriteTpidrurw (
 198   UINTN Value
 199   );
 200
 201 #endif // __ARM_V7_H__