ArmPkg/Include/Drivers/PL341Dmc.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef PL341DMC_H_
  16 #define PL341DMC_H_
  17
  18
  19 struct pl341_dmc_config {
  20     UINTN\s\sbase;           // base address for the controller
  21     UINTN\s\shas_qos;        // has QoS registers
  22     UINTN\s\smax_chip;       // number of memory chips accessible
  23     UINT32\s\srefresh_prd;
  24     UINT32\s\scas_latency;
  25     UINT32\s\swrite_latency;
  26     UINT32\s\st_mrd;
  27     UINT32\s\st_ras;
  28     UINT32\s\st_rc;
  29     UINT32\s\st_rcd;
  30     UINT32\s\st_rfc;
  31     UINT32\s\st_rp;
  32     UINT32\s\st_rrd;
  33     UINT32\s\st_wr;
  34     UINT32\s\st_wtr;
  35     UINT32\s\st_xp;
  36     UINT32\s\st_xsr;
  37     UINT32\s\st_esr;
  38     UINT32\s\smemory_cfg;
  39     UINT32\s\smemory_cfg2;
  40     UINT32\s\smemory_cfg3;
  41     UINT32\s\schip_cfg0;
  42     UINT32\s\schip_cfg1;
  43     UINT32\s\schip_cfg2;
  44     UINT32\s\schip_cfg3;
  45     UINT32\s\st_faw;
  46 };
  47
  48 /* Memory config bit fields */
  49 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_9      0x1
  50 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10     0x2
  51 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_11     0x3
  52 #define DMC_MEMORY_CONFIG_COLUMN_ADDRESS_12     0x4
  53 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_11        (0x0 << 3)
  54 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_12        (0x1 << 3)
  55 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_13        (0x2 << 3)
  56 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_14        (0x3 << 3)
  57 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_15        (0x4 << 3)
  58 #define DMC_MEMORY_CONFIG_ROW_ADDRESS_16        (0x5 << 3)
  59 #define DMC_MEMORY_CONFIG_BURST_2               (0x1 << 15)
  60 #define DMC_MEMORY_CONFIG_BURST_4               (0x2 << 15)
  61 #define DMC_MEMORY_CONFIG_BURST_8               (0x3 << 15)
  62 #define DMC_MEMORY_CONFIG_BURST_16              (0x4 << 15)
  63 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_1\s\s\s\s(0x0 << 21)
  64 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_2\s\s\s\s(0x1 << 21)
  65 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_3\s\s\s\s(0x2 << 21)
  66 #define DMC_MEMORY_CONFIG_ACTIVE_CHIP_4\s\s\s\s(0x3 << 21)
  67
  68 #define DMC_MEMORY_CFG2_CLK_ASYNC\s\s\s\s(0x0 << 0)
  69 #define DMC_MEMORY_CFG2_CLK_SYNC\s\s\s\s(0x1 << 0)
  70 #define DMC_MEMORY_CFG2_DQM_INIT\s\s\s\s(0x1 << 2)
  71 #define DMC_MEMORY_CFG2_CKE_INIT\s\s\s\s(0x1 << 3)
  72 #define DMC_MEMORY_CFG2_BANK_BITS_2\s\s\s\s(0x0 << 4)
  73 #define DMC_MEMORY_CFG2_BANK_BITS_3\s\s\s\s(0x3 << 4)
  74 #define DMC_MEMORY_CFG2_MEM_WIDTH_16\s\s\s\s(0x0 << 6)
  75 #define DMC_MEMORY_CFG2_MEM_WIDTH_32\s\s\s\s(0x1 << 6)
  76 #define DMC_MEMORY_CFG2_MEM_WIDTH_64\s\s\s\s(0x2 << 6)
  77 #define DMC_MEMORY_CFG2_MEM_WIDTH_RESERVED\s\s(0x3 << 6)
  78
  79
  80
  81 VOID PL341DmcInit(struct pl341_dmc_config *config);
  82
  83
  84 #endif /* PL341DMC_H_ */