ArmPkg/Include/Drivers/PL390Gic.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __PL390GIC_H
  16 #define __PL390GIC_H
  17
  18 //
  19 // GIC definitions
  20 //
  21
  22 // Distributor
  23 #define GIC_ICDDCR          0x000 // Distributor Control Register
  24 #define GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  25 #define GIC_ICDIIDR         0x008 // Implementer Identification Register
  26
  27 // each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)
  28 #define GIC_ICDISR          0x080 // Interrupt Security Registers
  29 #define GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  30 #define GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  31 #define GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  32 #define GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  33 #define GIC_ICDABR          0x300 // Active Bit Registers
  34
  35 // each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES
  36 #define GIC_ICDIPR          0x400 // Interrupt Priority Registers
  37
  38 // each reg base below repeats for VE_NUM_GIC_INTERRUPTS
  39 #define GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  40 #define GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  41
  42 // just one of these
  43 #define GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  44
  45 // Cpu interface
  46 #define GIC_ICCICR          0x00  // CPU Interface Control Register
  47 #define GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  48 #define GIC_ICCBPR          0x08  // Binary Point Register
  49 #define GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  50 #define GIC_ICCEIOR         0x10  // End Of Interrupt Register
  51 #define GIC_ICCRPR          0x14  // Running Priority Register
  52 #define GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  53 #define GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  54 #define GIC_ICCIDR          0xFC  // Identification Register
  55
  56 #define GIC_ICDSGIR_FILTER_TARGETLIST       0x0
  57 #define GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
  58 #define GIC_ICDSGIR_FILTER_ITSELF           0x2
  59
  60 //Bit-masks to configure the CPU Interface Control register
  61 #define GIC_ICCICR_ENABLE_SECURE(a)       ((a << 0) & 0x01)
  62 #define GIC_ICCICR_ENABLE_NS(a)           ((a << 1) & 0x02)
  63 #define GIC_ICCICR_ACK_CTL(a)             ((a << 2) & 0x04)
  64 #define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)
  65 #define GIC_ICCICR_USE_SBPR(a)            ((a << 4) & 0x10)
  66
  67
  68 //
  69 // GIC SEC interfaces
  70 //
  71 VOID
  72 EFIAPI
  73 PL390GicSetupNonSecure (
  74   IN  INTN          GicDistributorBase,
  75   IN  INTN          GicInterruptInterfaceBase
  76   );
  77
  78 VOID
  79 EFIAPI
  80 PL390GicEnableInterruptInterface (
  81   IN  INTN          GicInterruptInterfaceBase
  82   );
  83
  84 VOID
  85 EFIAPI
  86 PL390GicEnableDistributor (
  87   IN  INTN          GicDistributorBase
  88   );
  89
  90 VOID
  91 EFIAPI
  92 PL390GicSendSgiTo (
  93   IN  INTN          GicDistributorBase,
  94   IN  INTN          TargetListFilter,
  95   IN  INTN          CPUTargetList
  96   );
  97
  98 UINT32
  99 EFIAPI
 100 PL390GicAcknowledgeSgiFrom (
 101   IN  INTN          GicInterruptInterfaceBase,
 102   IN  INTN          CoreId
 103   );
 104
 105 UINT32
 106 EFIAPI
 107 PL390GicAcknowledgeSgi2From (
 108   IN  INTN          GicInterruptInterfaceBase,
 109   IN  INTN          CoreId,
 110   IN  INTN          SgiId
 111   );
 112
 113 UINTN
 114 EFIAPI
 115 PL390GicSetPriorityMask (
 116   IN  INTN          GicInterruptInterfaceBase,
 117   IN  INTN          PriorityMask
 118   );
 119
 120 #endif