ArmPkg/Include/IndustryStandard/ArmStdSmc.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2012-2017, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __ARM_STD_SMC_H__
  16 #define __ARM_STD_SMC_H__
  17
  18 /*
  19  * SMC function IDs for Standard Service queries
  20  */
  21
  22 #define ARM_SMC_ID_STD_CALL_COUNT     0x8400ff00
  23 #define ARM_SMC_ID_STD_UID            0x8400ff01
  24 /*                                    0x8400ff02 is reserved */
  25 #define ARM_SMC_ID_STD_REVISION       0x8400ff03
  26
  27 /*
  28  * The 'Standard Service Call UID' is supposed to return the Standard
  29  * Service UUID. This is a 128-bit value.
  30  */
  31 #define ARM_SMC_STD_UUID0       0x108d905b
  32 #define ARM_SMC_STD_UUID1       0x47e8f863
  33 #define ARM_SMC_STD_UUID2       0xfbc02dae
  34 #define ARM_SMC_STD_UUID3       0xe2f64156
  35
  36 /*
  37  * ARM Standard Service Calls revision numbers
  38  * The current revision is:  0.1
  39  */
  40 #define ARM_SMC_STD_REVISION_MAJOR    0x0
  41 #define ARM_SMC_STD_REVISION_MINOR    0x1
  42
  43 /*
  44  * Management Mode (MM) calls cover a subset of the Standard Service Call range.
  45  * The list below is not exhaustive.
  46  */
  47 #define ARM_SMC_ID_MM_VERSION_AARCH32              0x84000040
  48 #define ARM_SMC_ID_MM_VERSION_AARCH64              0xC4000040
  49
  50 // Request service from secure standalone MM environment
  51 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH32          0x84000041
  52 #define ARM_SMC_ID_MM_COMMUNICATE_AARCH64          0xC4000041
  53
  54 /* MM return error codes */
  55 #define ARM_SMC_MM_RET_SUCCESS              0
  56 #define ARM_SMC_MM_RET_NOT_SUPPORTED       -1
  57 #define ARM_SMC_MM_RET_INVALID_PARAMS      -2
  58 #define ARM_SMC_MM_RET_DENIED              -3
  59 #define ARM_SMC_MM_RET_NO_MEMORY           -4
  60
  61 /*
  62  * Power State Coordination Interface (PSCI) calls cover a subset of the
  63  * Standard Service Call range.
  64  * The list below is not exhaustive.
  65  */
  66 #define ARM_SMC_ID_PSCI_VERSION                0x84000000
  67 #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64    0xc4000001
  68 #define ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH32    0x84000001
  69 #define ARM_SMC_ID_PSCI_CPU_OFF                0x84000002
  70 #define ARM_SMC_ID_PSCI_CPU_ON_AARCH64         0xc4000003
  71 #define ARM_SMC_ID_PSCI_CPU_ON_AARCH32         0x84000003
  72 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH64  0xc4000004
  73 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_AARCH32  0x84000004
  74 #define ARM_SMC_ID_PSCI_MIGRATE_AARCH64        0xc4000005
  75 #define ARM_SMC_ID_PSCI_MIGRATE_AARCH32        0x84000005
  76 #define ARM_SMC_ID_PSCI_SYSTEM_OFF             0x84000008
  77 #define ARM_SMC_ID_PSCI_SYSTEM_RESET           0x84000009
  78
  79 /* The current PSCI version is:  0.2 */
  80 #define ARM_SMC_PSCI_VERSION_MAJOR  0
  81 #define ARM_SMC_PSCI_VERSION_MINOR  2
  82 #define ARM_SMC_PSCI_VERSION  \
  83   ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
  84
  85 /* PSCI return error codes */
  86 #define ARM_SMC_PSCI_RET_SUCCESS            0
  87 #define ARM_SMC_PSCI_RET_NOT_SUPPORTED      -1
  88 #define ARM_SMC_PSCI_RET_INVALID_PARAMS     -2
  89 #define ARM_SMC_PSCI_RET_DENIED             -3
  90 #define ARM_SMC_PSCI_RET_ALREADY_ON         -4
  91 #define ARM_SMC_PSCI_RET_ON_PENDING         -5
  92 #define ARM_SMC_PSCI_RET_INTERN_FAIL        -6
  93 #define ARM_SMC_PSCI_RET_NOT_PRESENT        -7
  94 #define ARM_SMC_PSCI_RET_DISABLED           -8
  95
  96 #define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
  97   ((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
  98
  99 #define ARM_SMC_PSCI_TARGET_CPU64(Aff3, Aff2, Aff1, Aff0) \
 100   ((((Aff3) & 0xFFULL) << 32) | (((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
 101
 102 #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId)  ((TargetId) & 0xFF)
 103 #define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId)  (((TargetId) >> 8) & 0xFF)
 104
 105 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0    0
 106 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1    1
 107 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2    2
 108 #define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3    3
 109
 110 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON          0
 111 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF         1
 112 #define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON_PENDING  2
 113
 114 #endif