ArmPkg/Include/Library/ArmGicLib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef __PL390GIC_H
  16 #define __PL390GIC_H
  17
  18 //
  19 // GIC definitions
  20 //
  21
  22 //
  23 // GIC Distributor
  24 //
  25 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register
  26 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
  27 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
  28
  29 // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
  30 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
  31 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
  32 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
  33 #define ARM_GIC_ICDSPR          0x200 // Interrupt Set-Pending Registers
  34 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
  35 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
  36
  37 // Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
  38 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
  39
  40 // Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
  41 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
  42 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
  43
  44 #define ARM_GIC_ICDPPISR        0xD00 // PPI Status register
  45
  46 // just one of these
  47 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
  48
  49 //
  50 // GIC Cpu interface
  51 //
  52 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register
  53 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register
  54 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register
  55 #define ARM_GIC_ICCIAR          0x0C  // Interrupt Acknowledge Register
  56 #define ARM_GIC_ICCEIOR         0x10  // End Of Interrupt Register
  57 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
  58 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
  59 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
  60 #define ARM_GIC_ICCIDR          0xFC  // Identification Register
  61
  62 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0
  63 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
  64 #define ARM_GIC_ICDSGIR_FILTER_ITSELF           0x2
  65
  66 // Bit-masks to configure the CPU Interface Control register
  67 #define ARM_GIC_ICCICR_ENABLE_SECURE            0x01
  68 #define ARM_GIC_ICCICR_ENABLE_NS                0x02
  69 #define ARM_GIC_ICCICR_ACK_CTL                  0x04
  70 #define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ     0x08
  71 #define ARM_GIC_ICCICR_USE_SBPR                 0x10
  72
  73
  74 //
  75 // GIC SEC interfaces
  76 //
  77 VOID
  78 EFIAPI
  79 ArmGicSetupNonSecure (
  80   IN  INTN          GicDistributorBase,
  81   IN  INTN          GicInterruptInterfaceBase
  82   );
  83
  84 VOID
  85 EFIAPI
  86 ArmGicEnableInterruptInterface (
  87   IN  INTN          GicInterruptInterfaceBase
  88   );
  89
  90 VOID
  91 EFIAPI
  92 ArmGicEnableDistributor (
  93   IN  INTN          GicDistributorBase
  94   );
  95
  96 VOID
  97 EFIAPI
  98 ArmGicSendSgiTo (
  99   IN  INTN          GicDistributorBase,
 100   IN  INTN          TargetListFilter,
 101   IN  INTN          CPUTargetList
 102   );
 103
 104 UINT32
 105 EFIAPI
 106 ArmGicAcknowledgeSgiFrom (
 107   IN  INTN          GicInterruptInterfaceBase,
 108   IN  INTN          CoreId
 109   );
 110
 111 UINT32
 112 EFIAPI
 113 ArmGicAcknowledgeSgi2From (
 114   IN  INTN          GicInterruptInterfaceBase,
 115   IN  INTN          CoreId,
 116   IN  INTN          SgiId
 117   );
 118
 119 UINTN
 120 EFIAPI
 121 ArmGicSetPriorityMask (
 122   IN  INTN          GicInterruptInterfaceBase,
 123   IN  INTN          PriorityMask
 124   );
 125
 126 #endif