ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __ARM_LIB__
  16 #define __ARM_LIB__
  17
  18 typedef enum {
  19   ARM_CACHE_TYPE_WRITE_BACK,
  20   ARM_CACHE_TYPE_UNKNOWN
  21 } ARM_CACHE_TYPE;
  22
  23 typedef enum {
  24   ARM_CACHE_ARCHITECTURE_UNIFIED,
  25   ARM_CACHE_ARCHITECTURE_SEPARATE,
  26   ARM_CACHE_ARCHITECTURE_UNKNOWN
  27 } ARM_CACHE_ARCHITECTURE;
  28
  29 typedef struct {
  30   ARM_CACHE_TYPE          Type;
  31   ARM_CACHE_ARCHITECTURE  Architecture;
  32   BOOLEAN                 DataCachePresent;
  33   UINTN                   DataCacheSize;
  34   UINTN                   DataCacheAssociativity;
  35   UINTN                   DataCacheLineLength;
  36   BOOLEAN                 InstructionCachePresent;
  37   UINTN                   InstructionCacheSize;
  38   UINTN                   InstructionCacheAssociativity;
  39   UINTN                   InstructionCacheLineLength;
  40 } ARM_CACHE_INFO;
  41
  42 typedef enum {
  43   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  44   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED,
  45   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  46   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK,
  47   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  48   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH,
  49   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  50   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
  51 } ARM_MEMORY_REGION_ATTRIBUTES;
  52
  53 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  54
  55 typedef struct {
  56   UINT32                        PhysicalBase;
  57   UINT32                        VirtualBase;
  58   UINT32                        Length;
  59   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  60 } ARM_MEMORY_REGION_DESCRIPTOR;
  61
  62 typedef VOID (*CACHE_OPERATION)(VOID);
  63 typedef VOID (*LINE_OPERATION)(UINTN);
  64
  65 typedef enum {
  66   ARM_PROCESSOR_MODE_USER       = 0x10,
  67   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  68   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  69   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  70   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  71   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  72   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  73   ARM_PROCESSOR_MODE_MASK       = 0x1F
  74 } ARM_PROCESSOR_MODE;
  75
  76 ARM_CACHE_TYPE
  77 EFIAPI
  78 ArmCacheType (
  79   VOID
  80   );
  81
  82 ARM_CACHE_ARCHITECTURE
  83 EFIAPI
  84 ArmCacheArchitecture (
  85   VOID
  86   );
  87
  88 VOID
  89 EFIAPI
  90 ArmCacheInformation (
  91   OUT ARM_CACHE_INFO  *CacheInfo
  92   );
  93
  94 BOOLEAN
  95 EFIAPI
  96 ArmDataCachePresent (
  97   VOID
  98   );
  99
 100 UINTN
 101 EFIAPI
 102 ArmDataCacheSize (
 103   VOID
 104   );
 105
 106 UINTN
 107 EFIAPI
 108 ArmDataCacheAssociativity (
 109   VOID
 110   );
 111
 112 UINTN
 113 EFIAPI
 114 ArmDataCacheLineLength (
 115   VOID
 116   );
 117
 118 BOOLEAN
 119 EFIAPI
 120 ArmInstructionCachePresent (
 121   VOID
 122   );
 123
 124 UINTN
 125 EFIAPI
 126 ArmInstructionCacheSize (
 127   VOID
 128   );
 129
 130 UINTN
 131 EFIAPI
 132 ArmInstructionCacheAssociativity (
 133   VOID
 134   );
 135
 136 UINTN
 137 EFIAPI
 138 ArmInstructionCacheLineLength (
 139   VOID
 140   );
 141
 142 UINT32
 143 EFIAPI
 144 Cp15IdCode (
 145   VOID
 146   );
 147
 148 UINT32
 149 EFIAPI
 150 Cp15CacheInfo (
 151   VOID
 152   );
 153
 154 BOOLEAN
 155 EFIAPI
 156 ArmIsMPCore (
 157   VOID
 158   );
 159
 160 VOID
 161 EFIAPI
 162 ArmInvalidateDataCache (
 163   VOID
 164   );
 165
 166
 167 VOID
 168 EFIAPI
 169 ArmCleanInvalidateDataCache (
 170   VOID
 171   );
 172
 173 VOID
 174 EFIAPI
 175 ArmCleanDataCache (
 176   VOID
 177   );
 178
 179 VOID
 180 EFIAPI
 181 ArmInvalidateInstructionCache (
 182   VOID
 183   );
 184
 185 VOID
 186 EFIAPI
 187 ArmInvalidateDataCacheEntryByMVA (
 188   IN  UINTN   Address
 189   );
 190
 191 VOID
 192 EFIAPI
 193 ArmCleanDataCacheEntryByMVA (
 194   IN  UINTN   Address
 195   );
 196
 197 VOID
 198 EFIAPI
 199 ArmCleanInvalidateDataCacheEntryByMVA (
 200   IN  UINTN   Address
 201   );
 202
 203 VOID
 204 EFIAPI
 205 ArmEnableDataCache (
 206   VOID
 207   );
 208
 209 VOID
 210 EFIAPI
 211 ArmDisableDataCache (
 212   VOID
 213   );
 214
 215 VOID
 216 EFIAPI
 217 ArmEnableInstructionCache (
 218   VOID
 219   );
 220
 221 VOID
 222 EFIAPI
 223 ArmDisableInstructionCache (
 224   VOID
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmEnableMmu (
 230   VOID
 231   );
 232
 233 VOID
 234 EFIAPI
 235 ArmDisableMmu (
 236   VOID
 237   );
 238
 239 VOID
 240 EFIAPI
 241 ArmDisableCachesAndMmu (
 242   VOID
 243   );
 244
 245 VOID
 246 EFIAPI
 247 ArmEnableInterrupts (
 248   VOID
 249   );
 250
 251 UINTN
 252 EFIAPI
 253 ArmDisableInterrupts (
 254   VOID
 255   );
 256
 257 BOOLEAN
 258 EFIAPI
 259 ArmGetInterruptState (
 260   VOID
 261   );
 262
 263 VOID
 264 EFIAPI
 265 ArmEnableFiq (
 266   VOID
 267   );
 268
 269 UINTN
 270 EFIAPI
 271 ArmDisableFiq (
 272   VOID
 273   );
 274
 275 BOOLEAN
 276 EFIAPI
 277 ArmGetFiqState (
 278   VOID
 279   );
 280
 281 VOID
 282 EFIAPI
 283 ArmInvalidateTlb (
 284   VOID
 285   );
 286
 287 VOID
 288 EFIAPI
 289 ArmUpdateTranslationTableEntry (
 290   IN  VOID     *TranslationTableEntry,
 291   IN  VOID     *Mva
 292   );
 293
 294 VOID
 295 EFIAPI
 296 ArmSetDomainAccessControl (
 297   IN  UINT32  Domain
 298   );
 299
 300 VOID
 301 EFIAPI
 302 ArmSetTTBR0 (
 303   IN  VOID  *TranslationTableBase
 304   );
 305
 306 VOID *
 307 EFIAPI
 308 ArmGetTTBR0BaseAddress (
 309   VOID
 310   );
 311
 312 VOID
 313 EFIAPI
 314 ArmConfigureMmu (
 315   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 316   OUT VOID                          **TranslationTableBase OPTIONAL,
 317   OUT UINTN                         *TranslationTableSize  OPTIONAL
 318   );
 319
 320 BOOLEAN
 321 EFIAPI
 322 ArmMmuEnabled (
 323   VOID
 324   );
 325
 326 VOID
 327 EFIAPI
 328 ArmSwitchProcessorMode (
 329   IN ARM_PROCESSOR_MODE Mode
 330   );
 331
 332 ARM_PROCESSOR_MODE
 333 EFIAPI
 334 ArmProcessorMode (
 335   VOID
 336   );
 337
 338 VOID
 339 EFIAPI
 340 ArmEnableBranchPrediction (
 341   VOID
 342   );
 343
 344 VOID
 345 EFIAPI
 346 ArmDisableBranchPrediction (
 347   VOID
 348   );
 349
 350 VOID
 351 EFIAPI
 352 ArmSetLowVectors (
 353   VOID
 354   );
 355
 356 VOID
 357 EFIAPI
 358 ArmSetHighVectors (
 359   VOID
 360   );
 361
 362 VOID
 363 EFIAPI
 364 ArmDataMemoryBarrier (
 365   VOID
 366   );
 367
 368 VOID
 369 EFIAPI
 370 ArmDataSyncronizationBarrier (
 371   VOID
 372   );
 373
 374 VOID
 375 EFIAPI
 376 ArmInstructionSynchronizationBarrier (
 377   VOID
 378   );
 379
 380
 381 #endif // __ARM_LIB__