ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef ARM_CPU_ARMv6
  22 #include <Chipset/ARM1176JZ-S.h>
  23 #else
  24 #include <Chipset/ArmV7.h>
  25 #endif
  26
  27 typedef enum {
  28   ARM_CACHE_TYPE_WRITE_BACK,
  29   ARM_CACHE_TYPE_UNKNOWN
  30 } ARM_CACHE_TYPE;
  31
  32 typedef enum {
  33   ARM_CACHE_ARCHITECTURE_UNIFIED,
  34   ARM_CACHE_ARCHITECTURE_SEPARATE,
  35   ARM_CACHE_ARCHITECTURE_UNKNOWN
  36 } ARM_CACHE_ARCHITECTURE;
  37
  38 typedef struct {
  39   ARM_CACHE_TYPE          Type;
  40   ARM_CACHE_ARCHITECTURE  Architecture;
  41   BOOLEAN                 DataCachePresent;
  42   UINTN                   DataCacheSize;
  43   UINTN                   DataCacheAssociativity;
  44   UINTN                   DataCacheLineLength;
  45   BOOLEAN                 InstructionCachePresent;
  46   UINTN                   InstructionCacheSize;
  47   UINTN                   InstructionCacheAssociativity;
  48   UINTN                   InstructionCacheLineLength;
  49 } ARM_CACHE_INFO;
  50
  51 /**
  52  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  53  *
  54  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  55  * be used in Secure World to distinguished Secure to Non-Secure memory.
  56  */
  57 typedef enum {
  58   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  59   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  60   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  61   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  62   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  63   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  64   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  66 } ARM_MEMORY_REGION_ATTRIBUTES;
  67
  68 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  69
  70 typedef struct {
  71   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  72   EFI_VIRTUAL_ADDRESS           VirtualBase;
  73   UINTN                         Length;
  74   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  75 } ARM_MEMORY_REGION_DESCRIPTOR;
  76
  77 typedef VOID (*CACHE_OPERATION)(VOID);
  78 typedef VOID (*LINE_OPERATION)(UINTN);
  79
  80 //
  81 // ARM Processor Mode
  82 //
  83 typedef enum {
  84   ARM_PROCESSOR_MODE_USER       = 0x10,
  85   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  86   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  87   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  88   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  89   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  90   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  91   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  92   ARM_PROCESSOR_MODE_MASK       = 0x1F
  93 } ARM_PROCESSOR_MODE;
  94
  95 //
  96 // ARM Cpu IDs
  97 //
  98 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  99 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
 100 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
 101 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
 102 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
 103 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
 104
 105 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
 106 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
 107 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
 108 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
 109 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
 110 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
 111
 112 //
 113 // ARM MP Core IDs
 114 //
 115 #define ARM_CORE_MASK         0xFF
 116 #define ARM_CLUSTER_MASK      (0xFF << 8)
 117 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 118 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 119 // Get the position of the core for the Stack Offset (4 Core per Cluster)
 120 //   Position = (ClusterId * 4) + CoreId
 121 #define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
 122 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 123
 124 ARM_CACHE_TYPE
 125 EFIAPI
 126 ArmCacheType (
 127   VOID
 128   );
 129
 130 ARM_CACHE_ARCHITECTURE
 131 EFIAPI
 132 ArmCacheArchitecture (
 133   VOID
 134   );
 135
 136 VOID
 137 EFIAPI
 138 ArmCacheInformation (
 139   OUT ARM_CACHE_INFO  *CacheInfo
 140   );
 141
 142 BOOLEAN
 143 EFIAPI
 144 ArmDataCachePresent (
 145   VOID
 146   );
 147
 148 UINTN
 149 EFIAPI
 150 ArmDataCacheSize (
 151   VOID
 152   );
 153
 154 UINTN
 155 EFIAPI
 156 ArmDataCacheAssociativity (
 157   VOID
 158   );
 159
 160 UINTN
 161 EFIAPI
 162 ArmDataCacheLineLength (
 163   VOID
 164   );
 165
 166 BOOLEAN
 167 EFIAPI
 168 ArmInstructionCachePresent (
 169   VOID
 170   );
 171
 172 UINTN
 173 EFIAPI
 174 ArmInstructionCacheSize (
 175   VOID
 176   );
 177
 178 UINTN
 179 EFIAPI
 180 ArmInstructionCacheAssociativity (
 181   VOID
 182   );
 183
 184 UINTN
 185 EFIAPI
 186 ArmInstructionCacheLineLength (
 187   VOID
 188   );
 189
 190 UINT32
 191 EFIAPI
 192 Cp15IdCode (
 193   VOID
 194   );
 195
 196 UINT32
 197 EFIAPI
 198 Cp15CacheInfo (
 199   VOID
 200   );
 201
 202 BOOLEAN
 203 EFIAPI
 204 ArmIsMpCore (
 205   VOID
 206   );
 207
 208 VOID
 209 EFIAPI
 210 ArmInvalidateDataCache (
 211   VOID
 212   );
 213
 214
 215 VOID
 216 EFIAPI
 217 ArmCleanInvalidateDataCache (
 218   VOID
 219   );
 220
 221 VOID
 222 EFIAPI
 223 ArmCleanDataCache (
 224   VOID
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmCleanDataCacheToPoU (
 230   VOID
 231   );
 232
 233 VOID
 234 EFIAPI
 235 ArmInvalidateInstructionCache (
 236   VOID
 237   );
 238
 239 VOID
 240 EFIAPI
 241 ArmInvalidateDataCacheEntryByMVA (
 242   IN  UINTN   Address
 243   );
 244
 245 VOID
 246 EFIAPI
 247 ArmCleanDataCacheEntryByMVA (
 248   IN  UINTN   Address
 249   );
 250
 251 VOID
 252 EFIAPI
 253 ArmCleanInvalidateDataCacheEntryByMVA (
 254   IN  UINTN   Address
 255   );
 256
 257 VOID
 258 EFIAPI
 259 ArmEnableDataCache (
 260   VOID
 261   );
 262
 263 VOID
 264 EFIAPI
 265 ArmDisableDataCache (
 266   VOID
 267   );
 268
 269 VOID
 270 EFIAPI
 271 ArmEnableInstructionCache (
 272   VOID
 273   );
 274
 275 VOID
 276 EFIAPI
 277 ArmDisableInstructionCache (
 278   VOID
 279   );
 280
 281 VOID
 282 EFIAPI
 283 ArmEnableMmu (
 284   VOID
 285   );
 286
 287 VOID
 288 EFIAPI
 289 ArmDisableMmu (
 290   VOID
 291   );
 292
 293 VOID
 294 EFIAPI
 295 ArmDisableCachesAndMmu (
 296   VOID
 297   );
 298
 299 VOID
 300 EFIAPI
 301 ArmInvalidateInstructionAndDataTlb (
 302   VOID
 303   );
 304
 305 VOID
 306 EFIAPI
 307 ArmEnableInterrupts (
 308   VOID
 309   );
 310
 311 UINTN
 312 EFIAPI
 313 ArmDisableInterrupts (
 314   VOID
 315   );
 316
 317 BOOLEAN
 318 EFIAPI
 319 ArmGetInterruptState (
 320   VOID
 321   );
 322
 323 UINTN
 324 EFIAPI
 325 ArmDisableIrq (
 326   VOID
 327   );
 328
 329 VOID
 330 EFIAPI
 331 ArmEnableIrq (
 332   VOID
 333   );
 334
 335 VOID
 336 EFIAPI
 337 ArmEnableFiq (
 338   VOID
 339   );
 340
 341 UINTN
 342 EFIAPI
 343 ArmDisableFiq (
 344   VOID
 345   );
 346
 347 BOOLEAN
 348 EFIAPI
 349 ArmGetFiqState (
 350   VOID
 351   );
 352
 353 VOID
 354 EFIAPI
 355 ArmInvalidateTlb (
 356   VOID
 357   );
 358
 359 VOID
 360 EFIAPI
 361 ArmUpdateTranslationTableEntry (
 362   IN  VOID     *TranslationTableEntry,
 363   IN  VOID     *Mva
 364   );
 365
 366 VOID
 367 EFIAPI
 368 ArmSetDomainAccessControl (
 369   IN  UINT32  Domain
 370   );
 371
 372 VOID
 373 EFIAPI
 374 ArmSetTTBR0 (
 375   IN  VOID  *TranslationTableBase
 376   );
 377
 378 VOID *
 379 EFIAPI
 380 ArmGetTTBR0BaseAddress (
 381   VOID
 382   );
 383
 384 VOID
 385 EFIAPI
 386 ArmConfigureMmu (
 387   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 388   OUT VOID                          **TranslationTableBase OPTIONAL,
 389   OUT UINTN                         *TranslationTableSize  OPTIONAL
 390   );
 391
 392 BOOLEAN
 393 EFIAPI
 394 ArmMmuEnabled (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmSwitchProcessorMode (
 401   IN ARM_PROCESSOR_MODE Mode
 402   );
 403
 404 ARM_PROCESSOR_MODE
 405 EFIAPI
 406 ArmProcessorMode (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmEnableBranchPrediction (
 413   VOID
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmDisableBranchPrediction (
 419   VOID
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmSetLowVectors (
 425   VOID
 426   );
 427
 428 VOID
 429 EFIAPI
 430 ArmSetHighVectors (
 431   VOID
 432   );
 433
 434 VOID
 435 EFIAPI
 436 ArmDataMemoryBarrier (
 437   VOID
 438   );
 439
 440 VOID
 441 EFIAPI
 442 ArmDataSyncronizationBarrier (
 443   VOID
 444   );
 445
 446 VOID
 447 EFIAPI
 448 ArmInstructionSynchronizationBarrier (
 449   VOID
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmWriteVBar (
 455   IN  UINT32   VectorBase
 456   );
 457
 458 UINT32
 459 EFIAPI
 460 ArmReadVBar (
 461   VOID
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmWriteAuxCr (
 467   IN  UINT32    Bit
 468   );
 469
 470 UINT32
 471 EFIAPI
 472 ArmReadAuxCr (
 473   VOID
 474   );
 475
 476 VOID
 477 EFIAPI
 478 ArmSetAuxCrBit (
 479   IN  UINT32    Bits
 480   );
 481
 482 VOID
 483 EFIAPI
 484 ArmUnsetAuxCrBit (
 485   IN  UINT32    Bits
 486   );
 487
 488 VOID
 489 EFIAPI
 490 ArmCallSEV (
 491   VOID
 492   );
 493
 494 VOID
 495 EFIAPI
 496 ArmCallWFE (
 497   VOID
 498   );
 499
 500 VOID
 501 EFIAPI
 502 ArmCallWFI (
 503   VOID
 504   );
 505
 506 UINTN
 507 EFIAPI
 508 ArmReadMpidr (
 509   VOID
 510   );
 511
 512 UINT32
 513 EFIAPI
 514 ArmReadCpacr (
 515   VOID
 516   );
 517
 518 VOID
 519 EFIAPI
 520 ArmWriteCpacr (
 521   IN  UINT32   Access
 522   );
 523
 524 VOID
 525 EFIAPI
 526 ArmEnableVFP (
 527   VOID
 528   );
 529
 530 UINT32
 531 EFIAPI
 532 ArmReadNsacr (
 533   VOID
 534   );
 535
 536 VOID
 537 EFIAPI
 538 ArmWriteNsacr (
 539   IN  UINT32   SetWayFormat
 540   );
 541
 542 UINT32
 543 EFIAPI
 544 ArmReadScr (
 545   VOID
 546   );
 547
 548 VOID
 549 EFIAPI
 550 ArmWriteScr (
 551   IN  UINT32   SetWayFormat
 552   );
 553
 554 UINT32
 555 EFIAPI
 556 ArmReadMVBar (
 557   VOID
 558   );
 559
 560 VOID
 561 EFIAPI
 562 ArmWriteMVBar (
 563   IN  UINT32   VectorMonitorBase
 564   );
 565
 566 UINT32
 567 EFIAPI
 568 ArmReadSctlr (
 569   VOID
 570   );
 571
 572 UINTN
 573 EFIAPI
 574 ArmReadHVBar (
 575   VOID
 576   );
 577
 578 VOID
 579 EFIAPI
 580 ArmWriteHVBar (
 581   IN  UINTN   HypModeVectorBase
 582   );
 583
 584 #endif // __ARM_LIB__