ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #include <Chipset/ArmV7.h>
  23 #elif defined(MDE_CPU_AARCH64)
  24   #include <Chipset/AArch64.h>
  25 #else
  26  #error "Unknown chipset."
  27 #endif
  28
  29 typedef enum {
  30   ARM_CACHE_TYPE_WRITE_BACK,
  31   ARM_CACHE_TYPE_UNKNOWN
  32 } ARM_CACHE_TYPE;
  33
  34 typedef enum {
  35   ARM_CACHE_ARCHITECTURE_UNIFIED,
  36   ARM_CACHE_ARCHITECTURE_SEPARATE,
  37   ARM_CACHE_ARCHITECTURE_UNKNOWN
  38 } ARM_CACHE_ARCHITECTURE;
  39
  40 typedef struct {
  41   ARM_CACHE_TYPE          Type;
  42   ARM_CACHE_ARCHITECTURE  Architecture;
  43   BOOLEAN                 DataCachePresent;
  44   UINTN                   DataCacheSize;
  45   UINTN                   DataCacheAssociativity;
  46   UINTN                   DataCacheLineLength;
  47   BOOLEAN                 InstructionCachePresent;
  48   UINTN                   InstructionCacheSize;
  49   UINTN                   InstructionCacheAssociativity;
  50   UINTN                   InstructionCacheLineLength;
  51 } ARM_CACHE_INFO;
  52
  53 /**
  54  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  55  *
  56  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  57  * be used in Secure World to distinguished Secure to Non-Secure memory.
  58  */
  59 typedef enum {
  60   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  61   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  62   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  63   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  64   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  66   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  67   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  68 } ARM_MEMORY_REGION_ATTRIBUTES;
  69
  70 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  71
  72 typedef struct {
  73   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  74   EFI_VIRTUAL_ADDRESS           VirtualBase;
  75   UINT64                        Length;
  76   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  77 } ARM_MEMORY_REGION_DESCRIPTOR;
  78
  79 typedef VOID (*CACHE_OPERATION)(VOID);
  80 typedef VOID (*LINE_OPERATION)(UINTN);
  81
  82 //
  83 // ARM Processor Mode
  84 //
  85 typedef enum {
  86   ARM_PROCESSOR_MODE_USER       = 0x10,
  87   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  88   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  89   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  90   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  91   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  92   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  93   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  94   ARM_PROCESSOR_MODE_MASK       = 0x1F
  95 } ARM_PROCESSOR_MODE;
  96
  97 //
  98 // ARM Cpu IDs
  99 //
 100 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
 101 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
 102 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
 103 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
 104 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
 105 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
 106
 107 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
 108 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
 109 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
 110 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
 111 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
 112 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
 113
 114 //
 115 // ARM MP Core IDs
 116 //
 117 #define ARM_CORE_AFF0         0xFF
 118 #define ARM_CORE_AFF1         (0xFF << 8)
 119 #define ARM_CORE_AFF2         (0xFF << 16)
 120 #define ARM_CORE_AFF3         (0xFFULL << 32)
 121
 122 #define ARM_CORE_MASK         ARM_CORE_AFF0
 123 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 124 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 125 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 126 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 127 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 128
 129 ARM_CACHE_TYPE
 130 EFIAPI
 131 ArmCacheType (
 132   VOID
 133   );
 134
 135 ARM_CACHE_ARCHITECTURE
 136 EFIAPI
 137 ArmCacheArchitecture (
 138   VOID
 139   );
 140
 141 VOID
 142 EFIAPI
 143 ArmCacheInformation (
 144   OUT ARM_CACHE_INFO  *CacheInfo
 145   );
 146
 147 BOOLEAN
 148 EFIAPI
 149 ArmDataCachePresent (
 150   VOID
 151   );
 152
 153 UINTN
 154 EFIAPI
 155 ArmDataCacheSize (
 156   VOID
 157   );
 158
 159 UINTN
 160 EFIAPI
 161 ArmDataCacheAssociativity (
 162   VOID
 163   );
 164
 165 UINTN
 166 EFIAPI
 167 ArmDataCacheLineLength (
 168   VOID
 169   );
 170
 171 BOOLEAN
 172 EFIAPI
 173 ArmInstructionCachePresent (
 174   VOID
 175   );
 176
 177 UINTN
 178 EFIAPI
 179 ArmInstructionCacheSize (
 180   VOID
 181   );
 182
 183 UINTN
 184 EFIAPI
 185 ArmInstructionCacheAssociativity (
 186   VOID
 187   );
 188
 189 UINTN
 190 EFIAPI
 191 ArmInstructionCacheLineLength (
 192   VOID
 193   );
 194
 195 UINTN
 196 EFIAPI
 197 ArmIsArchTimerImplemented (
 198   VOID
 199   );
 200
 201 UINTN
 202 EFIAPI
 203 ArmReadIdPfr0 (
 204   VOID
 205   );
 206
 207 UINTN
 208 EFIAPI
 209 ArmReadIdPfr1 (
 210   VOID
 211   );
 212
 213 UINTN
 214 EFIAPI
 215 ArmCacheInfo (
 216   VOID
 217   );
 218
 219 BOOLEAN
 220 EFIAPI
 221 ArmIsMpCore (
 222   VOID
 223   );
 224
 225 VOID
 226 EFIAPI
 227 ArmInvalidateDataCache (
 228   VOID
 229   );
 230
 231
 232 VOID
 233 EFIAPI
 234 ArmCleanInvalidateDataCache (
 235   VOID
 236   );
 237
 238 VOID
 239 EFIAPI
 240 ArmCleanDataCache (
 241   VOID
 242   );
 243
 244 VOID
 245 EFIAPI
 246 ArmCleanDataCacheToPoU (
 247   VOID
 248   );
 249
 250 VOID
 251 EFIAPI
 252 ArmInvalidateInstructionCache (
 253   VOID
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmInvalidateDataCacheEntryByMVA (
 259   IN  UINTN   Address
 260   );
 261
 262 VOID
 263 EFIAPI
 264 ArmCleanDataCacheEntryByMVA (
 265   IN  UINTN   Address
 266   );
 267
 268 VOID
 269 EFIAPI
 270 ArmCleanInvalidateDataCacheEntryByMVA (
 271   IN  UINTN   Address
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmInvalidateDataCacheEntryBySetWay (
 277   IN  UINTN  SetWayFormat
 278   );
 279
 280 VOID
 281 EFIAPI
 282 ArmCleanDataCacheEntryBySetWay (
 283   IN  UINTN  SetWayFormat
 284   );
 285
 286 VOID
 287 EFIAPI
 288 ArmCleanInvalidateDataCacheEntryBySetWay (
 289   IN  UINTN   SetWayFormat
 290   );
 291
 292 VOID
 293 EFIAPI
 294 ArmEnableDataCache (
 295   VOID
 296   );
 297
 298 VOID
 299 EFIAPI
 300 ArmDisableDataCache (
 301   VOID
 302   );
 303
 304 VOID
 305 EFIAPI
 306 ArmEnableInstructionCache (
 307   VOID
 308   );
 309
 310 VOID
 311 EFIAPI
 312 ArmDisableInstructionCache (
 313   VOID
 314   );
 315
 316 VOID
 317 EFIAPI
 318 ArmEnableMmu (
 319   VOID
 320   );
 321
 322 VOID
 323 EFIAPI
 324 ArmDisableMmu (
 325   VOID
 326   );
 327
 328 VOID
 329 EFIAPI
 330 ArmEnableCachesAndMmu (
 331   VOID
 332   );
 333
 334 VOID
 335 EFIAPI
 336 ArmDisableCachesAndMmu (
 337   VOID
 338   );
 339
 340 VOID
 341 EFIAPI
 342 ArmEnableInterrupts (
 343   VOID
 344   );
 345
 346 UINTN
 347 EFIAPI
 348 ArmDisableInterrupts (
 349   VOID
 350   );
 351
 352 BOOLEAN
 353 EFIAPI
 354 ArmGetInterruptState (
 355   VOID
 356   );
 357
 358 VOID
 359 EFIAPI
 360 ArmEnableAsynchronousAbort (
 361   VOID
 362   );
 363
 364 UINTN
 365 EFIAPI
 366 ArmDisableAsynchronousAbort (
 367   VOID
 368   );
 369
 370 VOID
 371 EFIAPI
 372 ArmEnableIrq (
 373   VOID
 374   );
 375
 376 UINTN
 377 EFIAPI
 378 ArmDisableIrq (
 379   VOID
 380   );
 381
 382 VOID
 383 EFIAPI
 384 ArmEnableFiq (
 385   VOID
 386   );
 387
 388 UINTN
 389 EFIAPI
 390 ArmDisableFiq (
 391   VOID
 392   );
 393
 394 BOOLEAN
 395 EFIAPI
 396 ArmGetFiqState (
 397   VOID
 398   );
 399
 400 /**
 401  * Invalidate Data and Instruction TLBs
 402  */
 403 VOID
 404 EFIAPI
 405 ArmInvalidateTlb (
 406   VOID
 407   );
 408
 409 VOID
 410 EFIAPI
 411 ArmUpdateTranslationTableEntry (
 412   IN  VOID     *TranslationTableEntry,
 413   IN  VOID     *Mva
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmSetDomainAccessControl (
 419   IN  UINT32  Domain
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmSetTTBR0 (
 425   IN  VOID  *TranslationTableBase
 426   );
 427
 428 VOID *
 429 EFIAPI
 430 ArmGetTTBR0BaseAddress (
 431   VOID
 432   );
 433
 434 RETURN_STATUS
 435 EFIAPI
 436 ArmConfigureMmu (
 437   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 438   OUT VOID                         **TranslationTableBase OPTIONAL,
 439   OUT UINTN                         *TranslationTableSize  OPTIONAL
 440   );
 441
 442 BOOLEAN
 443 EFIAPI
 444 ArmMmuEnabled (
 445   VOID
 446   );
 447
 448 VOID
 449 EFIAPI
 450 ArmEnableBranchPrediction (
 451   VOID
 452   );
 453
 454 VOID
 455 EFIAPI
 456 ArmDisableBranchPrediction (
 457   VOID
 458   );
 459
 460 VOID
 461 EFIAPI
 462 ArmSetLowVectors (
 463   VOID
 464   );
 465
 466 VOID
 467 EFIAPI
 468 ArmSetHighVectors (
 469   VOID
 470   );
 471
 472 VOID
 473 EFIAPI
 474 ArmDrainWriteBuffer (
 475   VOID
 476   );
 477
 478 VOID
 479 EFIAPI
 480 ArmDataMemoryBarrier (
 481   VOID
 482   );
 483
 484 VOID
 485 EFIAPI
 486 ArmDataSyncronizationBarrier (
 487   VOID
 488   );
 489
 490 VOID
 491 EFIAPI
 492 ArmInstructionSynchronizationBarrier (
 493   VOID
 494   );
 495
 496 VOID
 497 EFIAPI
 498 ArmWriteVBar (
 499   IN  UINTN   VectorBase
 500   );
 501
 502 UINTN
 503 EFIAPI
 504 ArmReadVBar (
 505   VOID
 506   );
 507
 508 VOID
 509 EFIAPI
 510 ArmWriteAuxCr (
 511   IN  UINT32    Bit
 512   );
 513
 514 UINT32
 515 EFIAPI
 516 ArmReadAuxCr (
 517   VOID
 518   );
 519
 520 VOID
 521 EFIAPI
 522 ArmSetAuxCrBit (
 523   IN  UINT32    Bits
 524   );
 525
 526 VOID
 527 EFIAPI
 528 ArmUnsetAuxCrBit (
 529   IN  UINT32    Bits
 530   );
 531
 532 VOID
 533 EFIAPI
 534 ArmCallSEV (
 535   VOID
 536   );
 537
 538 VOID
 539 EFIAPI
 540 ArmCallWFE (
 541   VOID
 542   );
 543
 544 VOID
 545 EFIAPI
 546 ArmCallWFI (
 547
 548   VOID
 549   );
 550
 551 UINTN
 552 EFIAPI
 553 ArmReadMpidr (
 554   VOID
 555   );
 556
 557 UINTN
 558 EFIAPI
 559 ArmReadMidr (
 560   VOID
 561   );
 562
 563 UINT32
 564 EFIAPI
 565 ArmReadCpacr (
 566   VOID
 567   );
 568
 569 VOID
 570 EFIAPI
 571 ArmWriteCpacr (
 572   IN  UINT32   Access
 573   );
 574
 575 VOID
 576 EFIAPI
 577 ArmEnableVFP (
 578   VOID
 579   );
 580
 581 /**
 582   Get the Secure Configuration Register value
 583
 584   @return   Value read from the Secure Configuration Register
 585
 586 **/
 587 UINT32
 588 EFIAPI
 589 ArmReadScr (
 590   VOID
 591   );
 592
 593 /**
 594   Set the Secure Configuration Register
 595
 596   @param Value   Value to write to the Secure Configuration Register
 597
 598 **/
 599 VOID
 600 EFIAPI
 601 ArmWriteScr (
 602   IN  UINT32   Value
 603   );
 604
 605 UINT32
 606 EFIAPI
 607 ArmReadMVBar (
 608   VOID
 609   );
 610
 611 VOID
 612 EFIAPI
 613 ArmWriteMVBar (
 614   IN  UINT32   VectorMonitorBase
 615   );
 616
 617 UINT32
 618 EFIAPI
 619 ArmReadSctlr (
 620   VOID
 621   );
 622
 623 UINTN
 624 EFIAPI
 625 ArmReadHVBar (
 626   VOID
 627   );
 628
 629 VOID
 630 EFIAPI
 631 ArmWriteHVBar (
 632   IN  UINTN   HypModeVectorBase
 633   );
 634
 635
 636 //
 637 // Helper functions for accessing CPU ACTLR
 638 //
 639
 640 UINTN
 641 EFIAPI
 642 ArmReadCpuActlr (
 643   VOID
 644   );
 645
 646 VOID
 647 EFIAPI
 648 ArmWriteCpuActlr (
 649   IN  UINTN Val
 650   );
 651
 652 VOID
 653 EFIAPI
 654 ArmSetCpuActlrBit (
 655   IN  UINTN    Bits
 656   );
 657
 658 VOID
 659 EFIAPI
 660 ArmUnsetCpuActlrBit (
 661   IN  UINTN    Bits
 662   );
 663
 664 RETURN_STATUS
 665 ArmSetMemoryRegionNoExec (
 666   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 667   IN  UINT64                    Length
 668   );
 669
 670 RETURN_STATUS
 671 ArmClearMemoryRegionNoExec (
 672   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 673   IN  UINT64                    Length
 674   );
 675
 676 RETURN_STATUS
 677 ArmSetMemoryRegionReadOnly (
 678   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 679   IN  UINT64                    Length
 680   );
 681
 682 RETURN_STATUS
 683 ArmClearMemoryRegionReadOnly (
 684   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 685   IN  UINT64                    Length
 686   );
 687
 688 #endif // __ARM_LIB__