3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Chipset/ARM1176JZ-S.h>
21 #include <Chipset/ArmV7.h>
25 ARM_CACHE_TYPE_WRITE_BACK
,
26 ARM_CACHE_TYPE_UNKNOWN
30 ARM_CACHE_ARCHITECTURE_UNIFIED
,
31 ARM_CACHE_ARCHITECTURE_SEPARATE
,
32 ARM_CACHE_ARCHITECTURE_UNKNOWN
33 } ARM_CACHE_ARCHITECTURE
;
37 ARM_CACHE_ARCHITECTURE Architecture
;
38 BOOLEAN DataCachePresent
;
40 UINTN DataCacheAssociativity
;
41 UINTN DataCacheLineLength
;
42 BOOLEAN InstructionCachePresent
;
43 UINTN InstructionCacheSize
;
44 UINTN InstructionCacheAssociativity
;
45 UINTN InstructionCacheLineLength
;
49 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
50 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED
,
51 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
52 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK
,
53 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
54 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH
,
55 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
56 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
57 } ARM_MEMORY_REGION_ATTRIBUTES
;
59 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
65 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
66 } ARM_MEMORY_REGION_DESCRIPTOR
;
68 typedef VOID (*CACHE_OPERATION
)(VOID
);
69 typedef VOID (*LINE_OPERATION
)(UINTN
);
72 ARM_PROCESSOR_MODE_USER
= 0x10,
73 ARM_PROCESSOR_MODE_FIQ
= 0x11,
74 ARM_PROCESSOR_MODE_IRQ
= 0x12,
75 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
76 ARM_PROCESSOR_MODE_ABORT
= 0x17,
77 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
78 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
79 ARM_PROCESSOR_MODE_MASK
= 0x1F
82 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
83 #define GET_CORE_ID(MpId) ((MpId) & 0x3)
84 #define GET_CLUSTER_ID(MpId) (((MpId) >> 6) & 0x3C)
85 // Get the position of the core for the Stack Offset (4 Core per Cluster)
86 // Position = (ClusterId * 4) + CoreId
87 #define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3))
88 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0x3)
96 ARM_CACHE_ARCHITECTURE
98 ArmCacheArchitecture (
104 ArmCacheInformation (
105 OUT ARM_CACHE_INFO
*CacheInfo
110 ArmDataCachePresent (
122 ArmDataCacheAssociativity (
128 ArmDataCacheLineLength (
134 ArmInstructionCachePresent (
140 ArmInstructionCacheSize (
146 ArmInstructionCacheAssociativity (
152 ArmInstructionCacheLineLength (
176 ArmInvalidateDataCache (
183 ArmCleanInvalidateDataCache (
195 ArmInvalidateInstructionCache (
201 ArmInvalidateDataCacheEntryByMVA (
207 ArmCleanDataCacheEntryByMVA (
213 ArmCleanInvalidateDataCacheEntryByMVA (
225 ArmDisableDataCache (
231 ArmEnableInstructionCache (
237 ArmDisableInstructionCache (
255 ArmDisableCachesAndMmu (
261 ArmInvalidateInstructionAndDataTlb (
267 ArmEnableInterrupts (
273 ArmDisableInterrupts (
279 ArmGetInterruptState (
309 ArmUpdateTranslationTableEntry (
310 IN VOID
*TranslationTableEntry
,
316 ArmSetDomainAccessControl (
323 IN VOID
*TranslationTableBase
328 ArmGetTTBR0BaseAddress (
335 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
336 OUT VOID
**TranslationTableBase OPTIONAL
,
337 OUT UINTN
*TranslationTableSize OPTIONAL
348 ArmSwitchProcessorMode (
349 IN ARM_PROCESSOR_MODE Mode
360 ArmEnableBranchPrediction (
366 ArmDisableBranchPrediction (
384 ArmDataMemoryBarrier (
390 ArmDataSyncronizationBarrier (
396 ArmInstructionSynchronizationBarrier (
457 IN UINT32 SetWayFormat
463 IN UINT32 SetWayFormat
469 IN UINT32 VectorMonitorBase
472 #endif // __ARM_LIB__