3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Uefi/UefiBaseType.h>
22 #include <Chipset/ArmV7.h>
23 #elif defined(MDE_CPU_AARCH64)
24 #include <Chipset/AArch64.h>
26 #error "Unknown chipset."
29 #define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
30 EFI_MEMORY_WT | EFI_MEMORY_WB | \
34 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
36 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
37 * be used in Secure World to distinguished Secure to Non-Secure memory.
40 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
41 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
42 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
43 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
45 // On some platforms, memory mapped flash region is designed as not supporting
46 // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special
48 // Do NOT use below two attributes if you are not sure.
49 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE
,
50 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE
,
52 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
53 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
54 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
55 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
56 } ARM_MEMORY_REGION_ATTRIBUTES
;
58 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
61 EFI_PHYSICAL_ADDRESS PhysicalBase
;
62 EFI_VIRTUAL_ADDRESS VirtualBase
;
64 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
65 } ARM_MEMORY_REGION_DESCRIPTOR
;
67 typedef VOID (*CACHE_OPERATION
)(VOID
);
68 typedef VOID (*LINE_OPERATION
)(UINTN
);
74 ARM_PROCESSOR_MODE_USER
= 0x10,
75 ARM_PROCESSOR_MODE_FIQ
= 0x11,
76 ARM_PROCESSOR_MODE_IRQ
= 0x12,
77 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
78 ARM_PROCESSOR_MODE_ABORT
= 0x17,
79 ARM_PROCESSOR_MODE_HYP
= 0x1A,
80 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
81 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
82 ARM_PROCESSOR_MODE_MASK
= 0x1F
88 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
89 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
90 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
91 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
92 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
93 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
95 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
96 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
97 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
98 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
99 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
100 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
105 #define ARM_CORE_AFF0 0xFF
106 #define ARM_CORE_AFF1 (0xFF << 8)
107 #define ARM_CORE_AFF2 (0xFF << 16)
108 #define ARM_CORE_AFF3 (0xFFULL << 32)
110 #define ARM_CORE_MASK ARM_CORE_AFF0
111 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
112 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
113 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
114 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
115 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
119 ArmDataCacheLineLength (
125 ArmInstructionCacheLineLength (
131 ArmCacheWritebackGranule (
137 ArmIsArchTimerImplemented (
167 ArmInvalidateDataCache (
174 ArmCleanInvalidateDataCache (
186 ArmInvalidateInstructionCache (
192 ArmInvalidateDataCacheEntryByMVA (
198 ArmCleanDataCacheEntryToPoUByMVA (
204 ArmInvalidateInstructionCacheEntryToPoUByMVA (
210 ArmCleanDataCacheEntryByMVA (
216 ArmCleanInvalidateDataCacheEntryByMVA (
222 ArmInvalidateDataCacheEntryBySetWay (
223 IN UINTN SetWayFormat
228 ArmCleanDataCacheEntryBySetWay (
229 IN UINTN SetWayFormat
234 ArmCleanInvalidateDataCacheEntryBySetWay (
235 IN UINTN SetWayFormat
246 ArmDisableDataCache (
252 ArmEnableInstructionCache (
258 ArmDisableInstructionCache (
276 ArmEnableCachesAndMmu (
282 ArmDisableCachesAndMmu (
288 ArmEnableInterrupts (
294 ArmDisableInterrupts (
300 ArmGetInterruptState (
306 ArmEnableAsynchronousAbort (
312 ArmDisableAsynchronousAbort (
347 * Invalidate Data and Instruction TLBs
357 ArmUpdateTranslationTableEntry (
358 IN VOID
*TranslationTableEntry
,
364 ArmSetDomainAccessControl (
371 IN VOID
*TranslationTableBase
382 ArmGetTTBR0BaseAddress (
394 ArmEnableBranchPrediction (
400 ArmDisableBranchPrediction (
418 ArmDataMemoryBarrier (
424 ArmDataSynchronizationBarrier (
430 ArmInstructionSynchronizationBarrier (
520 Get the Secure Configuration Register value
522 @return Value read from the Secure Configuration Register
532 Set the Secure Configuration Register
534 @param Value Value to write to the Secure Configuration Register
552 IN UINT32 VectorMonitorBase
576 IN UINTN HypModeVectorBase
581 // Helper functions for accessing CPU ACTLR
604 ArmUnsetCpuActlrBit (
609 // Accessors for the architected generic timer registers
612 #define ARM_ARCH_TIMER_ENABLE (1 << 0)
613 #define ARM_ARCH_TIMER_IMASK (1 << 1)
614 #define ARM_ARCH_TIMER_ISTATUS (1 << 2)
736 #endif // __ARM_LIB__