3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Uefi/UefiBaseType.h>
22 #include <Chipset/ARM1176JZ-S.h>
24 #include <Chipset/ArmV7.h>
28 ARM_CACHE_TYPE_WRITE_BACK
,
29 ARM_CACHE_TYPE_UNKNOWN
33 ARM_CACHE_ARCHITECTURE_UNIFIED
,
34 ARM_CACHE_ARCHITECTURE_SEPARATE
,
35 ARM_CACHE_ARCHITECTURE_UNKNOWN
36 } ARM_CACHE_ARCHITECTURE
;
40 ARM_CACHE_ARCHITECTURE Architecture
;
41 BOOLEAN DataCachePresent
;
43 UINTN DataCacheAssociativity
;
44 UINTN DataCacheLineLength
;
45 BOOLEAN InstructionCachePresent
;
46 UINTN InstructionCacheSize
;
47 UINTN InstructionCacheAssociativity
;
48 UINTN InstructionCacheLineLength
;
52 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
54 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
55 * be used in Secure World to distinguished Secure to Non-Secure memory.
58 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
59 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
60 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
61 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
62 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
63 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
64 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
65 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
66 } ARM_MEMORY_REGION_ATTRIBUTES
;
68 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
71 EFI_PHYSICAL_ADDRESS PhysicalBase
;
72 EFI_VIRTUAL_ADDRESS VirtualBase
;
74 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
75 } ARM_MEMORY_REGION_DESCRIPTOR
;
77 typedef VOID (*CACHE_OPERATION
)(VOID
);
78 typedef VOID (*LINE_OPERATION
)(UINTN
);
84 ARM_PROCESSOR_MODE_USER
= 0x10,
85 ARM_PROCESSOR_MODE_FIQ
= 0x11,
86 ARM_PROCESSOR_MODE_IRQ
= 0x12,
87 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
88 ARM_PROCESSOR_MODE_ABORT
= 0x17,
89 ARM_PROCESSOR_MODE_HYP
= 0x1A,
90 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
91 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
92 ARM_PROCESSOR_MODE_MASK
= 0x1F
98 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
99 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
100 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
101 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
102 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
103 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
105 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
106 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
107 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
108 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
109 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
110 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
115 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
116 #define ARM_CORE_MASK 0xFF
117 #define ARM_CLUSTER_MASK (0xFF << 8)
118 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
119 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
120 // Get the position of the core for the Stack Offset (4 Core per Cluster)
121 // Position = (ClusterId * 4) + CoreId
122 #define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
123 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
131 ARM_CACHE_ARCHITECTURE
133 ArmCacheArchitecture (
139 ArmCacheInformation (
140 OUT ARM_CACHE_INFO
*CacheInfo
145 ArmDataCachePresent (
157 ArmDataCacheAssociativity (
163 ArmDataCacheLineLength (
169 ArmInstructionCachePresent (
175 ArmInstructionCacheSize (
181 ArmInstructionCacheAssociativity (
187 ArmInstructionCacheLineLength (
211 ArmInvalidateDataCache (
218 ArmCleanInvalidateDataCache (
230 ArmCleanDataCacheToPoU (
236 ArmInvalidateInstructionCache (
242 ArmInvalidateDataCacheEntryByMVA (
248 ArmCleanDataCacheEntryByMVA (
254 ArmCleanInvalidateDataCacheEntryByMVA (
266 ArmDisableDataCache (
272 ArmEnableInstructionCache (
278 ArmDisableInstructionCache (
296 ArmDisableCachesAndMmu (
302 ArmInvalidateInstructionAndDataTlb (
308 ArmEnableInterrupts (
314 ArmDisableInterrupts (
320 ArmGetInterruptState (
350 ArmUpdateTranslationTableEntry (
351 IN VOID
*TranslationTableEntry
,
357 ArmSetDomainAccessControl (
364 IN VOID
*TranslationTableBase
369 ArmGetTTBR0BaseAddress (
376 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
377 OUT VOID
**TranslationTableBase OPTIONAL
,
378 OUT UINTN
*TranslationTableSize OPTIONAL
389 ArmSwitchProcessorMode (
390 IN ARM_PROCESSOR_MODE Mode
401 ArmEnableBranchPrediction (
407 ArmDisableBranchPrediction (
425 ArmDataMemoryBarrier (
431 ArmDataSyncronizationBarrier (
437 ArmInstructionSynchronizationBarrier (
528 IN UINT32 SetWayFormat
540 IN UINT32 SetWayFormat
552 IN UINT32 VectorMonitorBase
561 #endif // __ARM_LIB__