3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Uefi/UefiBaseType.h>
21 #include <Chipset/ARM1176JZ-S.h>
23 #include <Chipset/ArmV7.h>
27 ARM_CACHE_TYPE_WRITE_BACK
,
28 ARM_CACHE_TYPE_UNKNOWN
32 ARM_CACHE_ARCHITECTURE_UNIFIED
,
33 ARM_CACHE_ARCHITECTURE_SEPARATE
,
34 ARM_CACHE_ARCHITECTURE_UNKNOWN
35 } ARM_CACHE_ARCHITECTURE
;
39 ARM_CACHE_ARCHITECTURE Architecture
;
40 BOOLEAN DataCachePresent
;
42 UINTN DataCacheAssociativity
;
43 UINTN DataCacheLineLength
;
44 BOOLEAN InstructionCachePresent
;
45 UINTN InstructionCacheSize
;
46 UINTN InstructionCacheAssociativity
;
47 UINTN InstructionCacheLineLength
;
51 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
52 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED
,
53 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
54 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK
,
55 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
56 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH
,
57 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
58 ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
59 } ARM_MEMORY_REGION_ATTRIBUTES
;
61 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
64 EFI_PHYSICAL_ADDRESS PhysicalBase
;
65 EFI_VIRTUAL_ADDRESS VirtualBase
;
67 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
68 } ARM_MEMORY_REGION_DESCRIPTOR
;
70 typedef VOID (*CACHE_OPERATION
)(VOID
);
71 typedef VOID (*LINE_OPERATION
)(UINTN
);
74 ARM_PROCESSOR_MODE_USER
= 0x10,
75 ARM_PROCESSOR_MODE_FIQ
= 0x11,
76 ARM_PROCESSOR_MODE_IRQ
= 0x12,
77 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
78 ARM_PROCESSOR_MODE_ABORT
= 0x17,
79 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
80 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
81 ARM_PROCESSOR_MODE_MASK
= 0x1F
84 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
85 #define GET_CORE_ID(MpId) ((MpId) & 0xFF)
86 #define GET_CLUSTER_ID(MpId) (((MpId) >> 8) & 0xFF)
87 // Get the position of the core for the Stack Offset (4 Core per Cluster)
88 // Position = (ClusterId * 4) + CoreId
89 #define GET_CORE_POS(MpId) ((((MpId) >> 6) & 0xFF) + ((MpId) & 0xFF))
90 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & 0xFF)
98 ARM_CACHE_ARCHITECTURE
100 ArmCacheArchitecture (
106 ArmCacheInformation (
107 OUT ARM_CACHE_INFO
*CacheInfo
112 ArmDataCachePresent (
124 ArmDataCacheAssociativity (
130 ArmDataCacheLineLength (
136 ArmInstructionCachePresent (
142 ArmInstructionCacheSize (
148 ArmInstructionCacheAssociativity (
154 ArmInstructionCacheLineLength (
178 ArmInvalidateDataCache (
185 ArmCleanInvalidateDataCache (
197 ArmCleanDataCacheToPoU (
203 ArmInvalidateInstructionCache (
209 ArmInvalidateDataCacheEntryByMVA (
215 ArmCleanDataCacheEntryByMVA (
221 ArmCleanInvalidateDataCacheEntryByMVA (
233 ArmDisableDataCache (
239 ArmEnableInstructionCache (
245 ArmDisableInstructionCache (
263 ArmDisableCachesAndMmu (
269 ArmInvalidateInstructionAndDataTlb (
275 ArmEnableInterrupts (
281 ArmDisableInterrupts (
287 ArmGetInterruptState (
317 ArmUpdateTranslationTableEntry (
318 IN VOID
*TranslationTableEntry
,
324 ArmSetDomainAccessControl (
331 IN VOID
*TranslationTableBase
336 ArmGetTTBR0BaseAddress (
343 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
344 OUT VOID
**TranslationTableBase OPTIONAL
,
345 OUT UINTN
*TranslationTableSize OPTIONAL
356 ArmSwitchProcessorMode (
357 IN ARM_PROCESSOR_MODE Mode
368 ArmEnableBranchPrediction (
374 ArmDisableBranchPrediction (
392 ArmDataMemoryBarrier (
398 ArmDataSyncronizationBarrier (
404 ArmInstructionSynchronizationBarrier (
465 IN UINT32 SetWayFormat
471 IN UINT32 SetWayFormat
477 IN UINT32 VectorMonitorBase
480 #endif // __ARM_LIB__