ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #include <Chipset/ArmV7.h>
  23 #elif defined(MDE_CPU_AARCH64)
  24   #include <Chipset/AArch64.h>
  25 #else
  26  #error "Unknown chipset."
  27 #endif
  28
  29 /**
  30  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  31  *
  32  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  33  * be used in Secure World to distinguished Secure to Non-Secure memory.
  34  */
  35 typedef enum {
  36   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  37   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  38   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  39   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  40   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  41   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  42   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  43   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  44 } ARM_MEMORY_REGION_ATTRIBUTES;
  45
  46 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  47
  48 typedef struct {
  49   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  50   EFI_VIRTUAL_ADDRESS           VirtualBase;
  51   UINT64                        Length;
  52   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  53 } ARM_MEMORY_REGION_DESCRIPTOR;
  54
  55 typedef VOID (*CACHE_OPERATION)(VOID);
  56 typedef VOID (*LINE_OPERATION)(UINTN);
  57
  58 //
  59 // ARM Processor Mode
  60 //
  61 typedef enum {
  62   ARM_PROCESSOR_MODE_USER       = 0x10,
  63   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  64   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  65   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  66   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  67   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  68   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  69   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  70   ARM_PROCESSOR_MODE_MASK       = 0x1F
  71 } ARM_PROCESSOR_MODE;
  72
  73 //
  74 // ARM Cpu IDs
  75 //
  76 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  77 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  78 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  79 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  80 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  81 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  82
  83 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  84 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  85 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  86 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  87 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  88 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  89
  90 //
  91 // ARM MP Core IDs
  92 //
  93 #define ARM_CORE_AFF0         0xFF
  94 #define ARM_CORE_AFF1         (0xFF << 8)
  95 #define ARM_CORE_AFF2         (0xFF << 16)
  96 #define ARM_CORE_AFF3         (0xFFULL << 32)
  97
  98 #define ARM_CORE_MASK         ARM_CORE_AFF0
  99 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 100 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 101 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 102 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 103 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 104
 105 UINTN
 106 EFIAPI
 107 ArmDataCacheLineLength (
 108   VOID
 109   );
 110
 111 UINTN
 112 EFIAPI
 113 ArmInstructionCacheLineLength (
 114   VOID
 115   );
 116
 117 UINTN
 118 EFIAPI
 119 ArmCacheWritebackGranule (
 120   VOID
 121   );
 122
 123 UINTN
 124 EFIAPI
 125 ArmIsArchTimerImplemented (
 126   VOID
 127   );
 128
 129 UINTN
 130 EFIAPI
 131 ArmReadIdPfr0 (
 132   VOID
 133   );
 134
 135 UINTN
 136 EFIAPI
 137 ArmReadIdPfr1 (
 138   VOID
 139   );
 140
 141 UINTN
 142 EFIAPI
 143 ArmCacheInfo (
 144   VOID
 145   );
 146
 147 BOOLEAN
 148 EFIAPI
 149 ArmIsMpCore (
 150   VOID
 151   );
 152
 153 VOID
 154 EFIAPI
 155 ArmInvalidateDataCache (
 156   VOID
 157   );
 158
 159
 160 VOID
 161 EFIAPI
 162 ArmCleanInvalidateDataCache (
 163   VOID
 164   );
 165
 166 VOID
 167 EFIAPI
 168 ArmCleanDataCache (
 169   VOID
 170   );
 171
 172 VOID
 173 EFIAPI
 174 ArmInvalidateInstructionCache (
 175   VOID
 176   );
 177
 178 VOID
 179 EFIAPI
 180 ArmInvalidateDataCacheEntryByMVA (
 181   IN  UINTN   Address
 182   );
 183
 184 VOID
 185 EFIAPI
 186 ArmCleanDataCacheEntryToPoUByMVA (
 187   IN  UINTN   Address
 188   );
 189
 190 VOID
 191 EFIAPI
 192 ArmInvalidateInstructionCacheEntryToPoUByMVA (
 193   IN  UINTN   Address
 194   );
 195
 196 VOID
 197 EFIAPI
 198 ArmCleanDataCacheEntryByMVA (
 199 IN  UINTN   Address
 200 );
 201
 202 VOID
 203 EFIAPI
 204 ArmCleanInvalidateDataCacheEntryByMVA (
 205   IN  UINTN   Address
 206   );
 207
 208 VOID
 209 EFIAPI
 210 ArmInvalidateDataCacheEntryBySetWay (
 211   IN  UINTN  SetWayFormat
 212   );
 213
 214 VOID
 215 EFIAPI
 216 ArmCleanDataCacheEntryBySetWay (
 217   IN  UINTN  SetWayFormat
 218   );
 219
 220 VOID
 221 EFIAPI
 222 ArmCleanInvalidateDataCacheEntryBySetWay (
 223   IN  UINTN   SetWayFormat
 224   );
 225
 226 VOID
 227 EFIAPI
 228 ArmEnableDataCache (
 229   VOID
 230   );
 231
 232 VOID
 233 EFIAPI
 234 ArmDisableDataCache (
 235   VOID
 236   );
 237
 238 VOID
 239 EFIAPI
 240 ArmEnableInstructionCache (
 241   VOID
 242   );
 243
 244 VOID
 245 EFIAPI
 246 ArmDisableInstructionCache (
 247   VOID
 248   );
 249
 250 VOID
 251 EFIAPI
 252 ArmEnableMmu (
 253   VOID
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmDisableMmu (
 259   VOID
 260   );
 261
 262 VOID
 263 EFIAPI
 264 ArmEnableCachesAndMmu (
 265   VOID
 266   );
 267
 268 VOID
 269 EFIAPI
 270 ArmDisableCachesAndMmu (
 271   VOID
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmEnableInterrupts (
 277   VOID
 278   );
 279
 280 UINTN
 281 EFIAPI
 282 ArmDisableInterrupts (
 283   VOID
 284   );
 285
 286 BOOLEAN
 287 EFIAPI
 288 ArmGetInterruptState (
 289   VOID
 290   );
 291
 292 VOID
 293 EFIAPI
 294 ArmEnableAsynchronousAbort (
 295   VOID
 296   );
 297
 298 UINTN
 299 EFIAPI
 300 ArmDisableAsynchronousAbort (
 301   VOID
 302   );
 303
 304 VOID
 305 EFIAPI
 306 ArmEnableIrq (
 307   VOID
 308   );
 309
 310 UINTN
 311 EFIAPI
 312 ArmDisableIrq (
 313   VOID
 314   );
 315
 316 VOID
 317 EFIAPI
 318 ArmEnableFiq (
 319   VOID
 320   );
 321
 322 UINTN
 323 EFIAPI
 324 ArmDisableFiq (
 325   VOID
 326   );
 327
 328 BOOLEAN
 329 EFIAPI
 330 ArmGetFiqState (
 331   VOID
 332   );
 333
 334 /**
 335  * Invalidate Data and Instruction TLBs
 336  */
 337 VOID
 338 EFIAPI
 339 ArmInvalidateTlb (
 340   VOID
 341   );
 342
 343 VOID
 344 EFIAPI
 345 ArmUpdateTranslationTableEntry (
 346   IN  VOID     *TranslationTableEntry,
 347   IN  VOID     *Mva
 348   );
 349
 350 VOID
 351 EFIAPI
 352 ArmSetDomainAccessControl (
 353   IN  UINT32  Domain
 354   );
 355
 356 VOID
 357 EFIAPI
 358 ArmSetTTBR0 (
 359   IN  VOID  *TranslationTableBase
 360   );
 361
 362 VOID
 363 EFIAPI
 364 ArmSetTTBCR (
 365   IN  UINT32 Bits
 366   );
 367
 368 VOID *
 369 EFIAPI
 370 ArmGetTTBR0BaseAddress (
 371   VOID
 372   );
 373
 374 BOOLEAN
 375 EFIAPI
 376 ArmMmuEnabled (
 377   VOID
 378   );
 379
 380 VOID
 381 EFIAPI
 382 ArmEnableBranchPrediction (
 383   VOID
 384   );
 385
 386 VOID
 387 EFIAPI
 388 ArmDisableBranchPrediction (
 389   VOID
 390   );
 391
 392 VOID
 393 EFIAPI
 394 ArmSetLowVectors (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmSetHighVectors (
 401   VOID
 402   );
 403
 404 VOID
 405 EFIAPI
 406 ArmDataMemoryBarrier (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmDataSynchronizationBarrier (
 413   VOID
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmInstructionSynchronizationBarrier (
 419   VOID
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmWriteVBar (
 425   IN  UINTN   VectorBase
 426   );
 427
 428 UINTN
 429 EFIAPI
 430 ArmReadVBar (
 431   VOID
 432   );
 433
 434 VOID
 435 EFIAPI
 436 ArmWriteAuxCr (
 437   IN  UINT32    Bit
 438   );
 439
 440 UINT32
 441 EFIAPI
 442 ArmReadAuxCr (
 443   VOID
 444   );
 445
 446 VOID
 447 EFIAPI
 448 ArmSetAuxCrBit (
 449   IN  UINT32    Bits
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmUnsetAuxCrBit (
 455   IN  UINT32    Bits
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmCallSEV (
 461   VOID
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmCallWFE (
 467   VOID
 468   );
 469
 470 VOID
 471 EFIAPI
 472 ArmCallWFI (
 473
 474   VOID
 475   );
 476
 477 UINTN
 478 EFIAPI
 479 ArmReadMpidr (
 480   VOID
 481   );
 482
 483 UINTN
 484 EFIAPI
 485 ArmReadMidr (
 486   VOID
 487   );
 488
 489 UINT32
 490 EFIAPI
 491 ArmReadCpacr (
 492   VOID
 493   );
 494
 495 VOID
 496 EFIAPI
 497 ArmWriteCpacr (
 498   IN  UINT32   Access
 499   );
 500
 501 VOID
 502 EFIAPI
 503 ArmEnableVFP (
 504   VOID
 505   );
 506
 507 /**
 508   Get the Secure Configuration Register value
 509
 510   @return   Value read from the Secure Configuration Register
 511
 512 **/
 513 UINT32
 514 EFIAPI
 515 ArmReadScr (
 516   VOID
 517   );
 518
 519 /**
 520   Set the Secure Configuration Register
 521
 522   @param Value   Value to write to the Secure Configuration Register
 523
 524 **/
 525 VOID
 526 EFIAPI
 527 ArmWriteScr (
 528   IN  UINT32   Value
 529   );
 530
 531 UINT32
 532 EFIAPI
 533 ArmReadMVBar (
 534   VOID
 535   );
 536
 537 VOID
 538 EFIAPI
 539 ArmWriteMVBar (
 540   IN  UINT32   VectorMonitorBase
 541   );
 542
 543 UINT32
 544 EFIAPI
 545 ArmReadSctlr (
 546   VOID
 547   );
 548
 549 UINTN
 550 EFIAPI
 551 ArmReadHVBar (
 552   VOID
 553   );
 554
 555 VOID
 556 EFIAPI
 557 ArmWriteHVBar (
 558   IN  UINTN   HypModeVectorBase
 559   );
 560
 561
 562 //
 563 // Helper functions for accessing CPU ACTLR
 564 //
 565
 566 UINTN
 567 EFIAPI
 568 ArmReadCpuActlr (
 569   VOID
 570   );
 571
 572 VOID
 573 EFIAPI
 574 ArmWriteCpuActlr (
 575   IN  UINTN Val
 576   );
 577
 578 VOID
 579 EFIAPI
 580 ArmSetCpuActlrBit (
 581   IN  UINTN    Bits
 582   );
 583
 584 VOID
 585 EFIAPI
 586 ArmUnsetCpuActlrBit (
 587   IN  UINTN    Bits
 588   );
 589
 590 //
 591 // Accessors for the architected generic timer registers
 592 //
 593
 594 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 595 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 596 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 597
 598 UINTN
 599 EFIAPI
 600 ArmReadCntFrq (
 601   VOID
 602   );
 603
 604 VOID
 605 EFIAPI
 606 ArmWriteCntFrq (
 607   UINTN   FreqInHz
 608   );
 609
 610 UINT64
 611 EFIAPI
 612 ArmReadCntPct (
 613   VOID
 614   );
 615
 616 UINTN
 617 EFIAPI
 618 ArmReadCntkCtl (
 619   VOID
 620   );
 621
 622 VOID
 623 EFIAPI
 624 ArmWriteCntkCtl (
 625   UINTN   Val
 626   );
 627
 628 UINTN
 629 EFIAPI
 630 ArmReadCntpTval (
 631   VOID
 632   );
 633
 634 VOID
 635 EFIAPI
 636 ArmWriteCntpTval (
 637   UINTN   Val
 638   );
 639
 640 UINTN
 641 EFIAPI
 642 ArmReadCntpCtl (
 643   VOID
 644   );
 645
 646 VOID
 647 EFIAPI
 648 ArmWriteCntpCtl (
 649   UINTN   Val
 650   );
 651
 652 UINTN
 653 EFIAPI
 654 ArmReadCntvTval (
 655   VOID
 656   );
 657
 658 VOID
 659 EFIAPI
 660 ArmWriteCntvTval (
 661   UINTN   Val
 662   );
 663
 664 UINTN
 665 EFIAPI
 666 ArmReadCntvCtl (
 667   VOID
 668   );
 669
 670 VOID
 671 EFIAPI
 672 ArmWriteCntvCtl (
 673   UINTN   Val
 674   );
 675
 676 UINT64
 677 EFIAPI
 678 ArmReadCntvCt (
 679   VOID
 680   );
 681
 682 UINT64
 683 EFIAPI
 684 ArmReadCntpCval (
 685   VOID
 686   );
 687
 688 VOID
 689 EFIAPI
 690 ArmWriteCntpCval (
 691   UINT64   Val
 692   );
 693
 694 UINT64
 695 EFIAPI
 696 ArmReadCntvCval (
 697   VOID
 698   );
 699
 700 VOID
 701 EFIAPI
 702 ArmWriteCntvCval (
 703   UINT64   Val
 704   );
 705
 706 UINT64
 707 EFIAPI
 708 ArmReadCntvOff (
 709   VOID
 710   );
 711
 712 VOID
 713 EFIAPI
 714 ArmWriteCntvOff (
 715   UINT64   Val
 716   );
 717
 718 #endif // __ARM_LIB__