ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef ARM_CPU_ARMv6
  22 #include <Chipset/ARM1176JZ-S.h>
  23 #else
  24 #include <Chipset/ArmV7.h>
  25 #endif
  26
  27 typedef enum {
  28   ARM_CACHE_TYPE_WRITE_BACK,
  29   ARM_CACHE_TYPE_UNKNOWN
  30 } ARM_CACHE_TYPE;
  31
  32 typedef enum {
  33   ARM_CACHE_ARCHITECTURE_UNIFIED,
  34   ARM_CACHE_ARCHITECTURE_SEPARATE,
  35   ARM_CACHE_ARCHITECTURE_UNKNOWN
  36 } ARM_CACHE_ARCHITECTURE;
  37
  38 typedef struct {
  39   ARM_CACHE_TYPE          Type;
  40   ARM_CACHE_ARCHITECTURE  Architecture;
  41   BOOLEAN                 DataCachePresent;
  42   UINTN                   DataCacheSize;
  43   UINTN                   DataCacheAssociativity;
  44   UINTN                   DataCacheLineLength;
  45   BOOLEAN                 InstructionCachePresent;
  46   UINTN                   InstructionCacheSize;
  47   UINTN                   InstructionCacheAssociativity;
  48   UINTN                   InstructionCacheLineLength;
  49 } ARM_CACHE_INFO;
  50
  51 /**
  52  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  53  *
  54  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  55  * be used in Secure World to distinguished Secure to Non-Secure memory.
  56  */
  57 typedef enum {
  58   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  59   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  60   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  61   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  62   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  63   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  64   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  66 } ARM_MEMORY_REGION_ATTRIBUTES;
  67
  68 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  69
  70 typedef struct {
  71   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  72   EFI_VIRTUAL_ADDRESS           VirtualBase;
  73   UINTN                         Length;
  74   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  75 } ARM_MEMORY_REGION_DESCRIPTOR;
  76
  77 typedef VOID (*CACHE_OPERATION)(VOID);
  78 typedef VOID (*LINE_OPERATION)(UINTN);
  79
  80 typedef enum {
  81   ARM_PROCESSOR_MODE_USER       = 0x10,
  82   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  83   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  84   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  85   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  86   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  87   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  88   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  89   ARM_PROCESSOR_MODE_MASK       = 0x1F
  90 } ARM_PROCESSOR_MODE;
  91
  92
  93 //
  94 // ARM MP Core IDs
  95 //
  96 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
  97 #define ARM_CORE_MASK         0xFF
  98 #define ARM_CLUSTER_MASK      (0xFF << 8)
  99 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 100 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 101 // Get the position of the core for the Stack Offset (4 Core per Cluster)
 102 //   Position = (ClusterId * 4) + CoreId
 103 #define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
 104 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 105
 106 ARM_CACHE_TYPE
 107 EFIAPI
 108 ArmCacheType (
 109   VOID
 110   );
 111
 112 ARM_CACHE_ARCHITECTURE
 113 EFIAPI
 114 ArmCacheArchitecture (
 115   VOID
 116   );
 117
 118 VOID
 119 EFIAPI
 120 ArmCacheInformation (
 121   OUT ARM_CACHE_INFO  *CacheInfo
 122   );
 123
 124 BOOLEAN
 125 EFIAPI
 126 ArmDataCachePresent (
 127   VOID
 128   );
 129
 130 UINTN
 131 EFIAPI
 132 ArmDataCacheSize (
 133   VOID
 134   );
 135
 136 UINTN
 137 EFIAPI
 138 ArmDataCacheAssociativity (
 139   VOID
 140   );
 141
 142 UINTN
 143 EFIAPI
 144 ArmDataCacheLineLength (
 145   VOID
 146   );
 147
 148 BOOLEAN
 149 EFIAPI
 150 ArmInstructionCachePresent (
 151   VOID
 152   );
 153
 154 UINTN
 155 EFIAPI
 156 ArmInstructionCacheSize (
 157   VOID
 158   );
 159
 160 UINTN
 161 EFIAPI
 162 ArmInstructionCacheAssociativity (
 163   VOID
 164   );
 165
 166 UINTN
 167 EFIAPI
 168 ArmInstructionCacheLineLength (
 169   VOID
 170   );
 171
 172 UINT32
 173 EFIAPI
 174 Cp15IdCode (
 175   VOID
 176   );
 177
 178 UINT32
 179 EFIAPI
 180 Cp15CacheInfo (
 181   VOID
 182   );
 183
 184 BOOLEAN
 185 EFIAPI
 186 ArmIsMpCore (
 187   VOID
 188   );
 189
 190 VOID
 191 EFIAPI
 192 ArmInvalidateDataCache (
 193   VOID
 194   );
 195
 196
 197 VOID
 198 EFIAPI
 199 ArmCleanInvalidateDataCache (
 200   VOID
 201   );
 202
 203 VOID
 204 EFIAPI
 205 ArmCleanDataCache (
 206   VOID
 207   );
 208
 209 VOID
 210 EFIAPI
 211 ArmCleanDataCacheToPoU (
 212   VOID
 213   );
 214
 215 VOID
 216 EFIAPI
 217 ArmInvalidateInstructionCache (
 218   VOID
 219   );
 220
 221 VOID
 222 EFIAPI
 223 ArmInvalidateDataCacheEntryByMVA (
 224   IN  UINTN   Address
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmCleanDataCacheEntryByMVA (
 230   IN  UINTN   Address
 231   );
 232
 233 VOID
 234 EFIAPI
 235 ArmCleanInvalidateDataCacheEntryByMVA (
 236   IN  UINTN   Address
 237   );
 238
 239 VOID
 240 EFIAPI
 241 ArmEnableDataCache (
 242   VOID
 243   );
 244
 245 VOID
 246 EFIAPI
 247 ArmDisableDataCache (
 248   VOID
 249   );
 250
 251 VOID
 252 EFIAPI
 253 ArmEnableInstructionCache (
 254   VOID
 255   );
 256
 257 VOID
 258 EFIAPI
 259 ArmDisableInstructionCache (
 260   VOID
 261   );
 262
 263 VOID
 264 EFIAPI
 265 ArmEnableMmu (
 266   VOID
 267   );
 268
 269 VOID
 270 EFIAPI
 271 ArmDisableMmu (
 272   VOID
 273   );
 274
 275 VOID
 276 EFIAPI
 277 ArmDisableCachesAndMmu (
 278   VOID
 279   );
 280
 281 VOID
 282 EFIAPI
 283 ArmInvalidateInstructionAndDataTlb (
 284   VOID
 285   );
 286
 287 VOID
 288 EFIAPI
 289 ArmEnableInterrupts (
 290   VOID
 291   );
 292
 293 UINTN
 294 EFIAPI
 295 ArmDisableInterrupts (
 296   VOID
 297   );
 298
 299 BOOLEAN
 300 EFIAPI
 301 ArmGetInterruptState (
 302   VOID
 303   );
 304
 305 VOID
 306 EFIAPI
 307 ArmEnableFiq (
 308   VOID
 309   );
 310
 311 UINTN
 312 EFIAPI
 313 ArmDisableFiq (
 314   VOID
 315   );
 316
 317 BOOLEAN
 318 EFIAPI
 319 ArmGetFiqState (
 320   VOID
 321   );
 322
 323 VOID
 324 EFIAPI
 325 ArmInvalidateTlb (
 326   VOID
 327   );
 328
 329 VOID
 330 EFIAPI
 331 ArmUpdateTranslationTableEntry (
 332   IN  VOID     *TranslationTableEntry,
 333   IN  VOID     *Mva
 334   );
 335
 336 VOID
 337 EFIAPI
 338 ArmSetDomainAccessControl (
 339   IN  UINT32  Domain
 340   );
 341
 342 VOID
 343 EFIAPI
 344 ArmSetTTBR0 (
 345   IN  VOID  *TranslationTableBase
 346   );
 347
 348 VOID *
 349 EFIAPI
 350 ArmGetTTBR0BaseAddress (
 351   VOID
 352   );
 353
 354 VOID
 355 EFIAPI
 356 ArmConfigureMmu (
 357   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 358   OUT VOID                          **TranslationTableBase OPTIONAL,
 359   OUT UINTN                         *TranslationTableSize  OPTIONAL
 360   );
 361
 362 BOOLEAN
 363 EFIAPI
 364 ArmMmuEnabled (
 365   VOID
 366   );
 367
 368 VOID
 369 EFIAPI
 370 ArmSwitchProcessorMode (
 371   IN ARM_PROCESSOR_MODE Mode
 372   );
 373
 374 ARM_PROCESSOR_MODE
 375 EFIAPI
 376 ArmProcessorMode (
 377   VOID
 378   );
 379
 380 VOID
 381 EFIAPI
 382 ArmEnableBranchPrediction (
 383   VOID
 384   );
 385
 386 VOID
 387 EFIAPI
 388 ArmDisableBranchPrediction (
 389   VOID
 390   );
 391
 392 VOID
 393 EFIAPI
 394 ArmSetLowVectors (
 395   VOID
 396   );
 397
 398 VOID
 399 EFIAPI
 400 ArmSetHighVectors (
 401   VOID
 402   );
 403
 404 VOID
 405 EFIAPI
 406 ArmDataMemoryBarrier (
 407   VOID
 408   );
 409
 410 VOID
 411 EFIAPI
 412 ArmDataSyncronizationBarrier (
 413   VOID
 414   );
 415
 416 VOID
 417 EFIAPI
 418 ArmInstructionSynchronizationBarrier (
 419   VOID
 420   );
 421
 422 VOID
 423 EFIAPI
 424 ArmWriteVBar (
 425   IN  UINT32   VectorBase
 426   );
 427
 428 UINT32
 429 EFIAPI
 430 ArmReadVBar (
 431   VOID
 432   );
 433
 434 VOID
 435 EFIAPI
 436 ArmWriteAuxCr (
 437   IN  UINT32    Bit
 438   );
 439
 440 UINT32
 441 EFIAPI
 442 ArmReadAuxCr (
 443   VOID
 444   );
 445
 446 VOID
 447 EFIAPI
 448 ArmSetAuxCrBit (
 449   IN  UINT32    Bits
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmUnsetAuxCrBit (
 455   IN  UINT32    Bits
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmCallSEV (
 461   VOID
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmCallWFE (
 467   VOID
 468   );
 469
 470 VOID
 471 EFIAPI
 472 ArmCallWFI (
 473   VOID
 474   );
 475
 476 UINTN
 477 EFIAPI
 478 ArmReadMpidr (
 479   VOID
 480   );
 481
 482 UINT32
 483 EFIAPI
 484 ArmReadCpacr (
 485   VOID
 486   );
 487
 488 VOID
 489 EFIAPI
 490 ArmWriteCpacr (
 491   IN  UINT32   Access
 492   );
 493
 494 VOID
 495 EFIAPI
 496 ArmEnableVFP (
 497   VOID
 498   );
 499
 500 UINT32
 501 EFIAPI
 502 ArmReadNsacr (
 503   VOID
 504   );
 505
 506 VOID
 507 EFIAPI
 508 ArmWriteNsacr (
 509   IN  UINT32   SetWayFormat
 510   );
 511
 512 UINT32
 513 EFIAPI
 514 ArmReadScr (
 515   VOID
 516   );
 517
 518 VOID
 519 EFIAPI
 520 ArmWriteScr (
 521   IN  UINT32   SetWayFormat
 522   );
 523
 524 UINT32
 525 EFIAPI
 526 ArmReadMVBar (
 527   VOID
 528   );
 529
 530 VOID
 531 EFIAPI
 532 ArmWriteMVBar (
 533   IN  UINT32   VectorMonitorBase
 534   );
 535
 536 UINT32
 537 EFIAPI
 538 ArmReadSctlr (
 539   VOID
 540   );
 541
 542 #endif // __ARM_LIB__