ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __ARM_LIB__
  16 #define __ARM_LIB__
  17
  18 #include <Uefi/UefiBaseType.h>
  19
  20 #ifdef ARM_CPU_ARMv6
  21 #include <Chipset/ARM1176JZ-S.h>
  22 #else
  23 #include <Chipset/ArmV7.h>
  24 #endif
  25
  26 typedef enum {
  27   ARM_CACHE_TYPE_WRITE_BACK,
  28   ARM_CACHE_TYPE_UNKNOWN
  29 } ARM_CACHE_TYPE;
  30
  31 typedef enum {
  32   ARM_CACHE_ARCHITECTURE_UNIFIED,
  33   ARM_CACHE_ARCHITECTURE_SEPARATE,
  34   ARM_CACHE_ARCHITECTURE_UNKNOWN
  35 } ARM_CACHE_ARCHITECTURE;
  36
  37 typedef struct {
  38   ARM_CACHE_TYPE          Type;
  39   ARM_CACHE_ARCHITECTURE  Architecture;
  40   BOOLEAN                 DataCachePresent;
  41   UINTN                   DataCacheSize;
  42   UINTN                   DataCacheAssociativity;
  43   UINTN                   DataCacheLineLength;
  44   BOOLEAN                 InstructionCachePresent;
  45   UINTN                   InstructionCacheSize;
  46   UINTN                   InstructionCacheAssociativity;
  47   UINTN                   InstructionCacheLineLength;
  48 } ARM_CACHE_INFO;
  49
  50 typedef enum {
  51   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  52   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_UNCACHED_UNBUFFERED,
  53   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  54   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_BACK,
  55   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  56   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_WRITE_THROUGH,
  57   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  58   ARM_MEMORY_REGION_ATTRIBUTE_SECURE_DEVICE
  59 } ARM_MEMORY_REGION_ATTRIBUTES;
  60
  61 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  62
  63 typedef struct {
  64   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  65   EFI_VIRTUAL_ADDRESS           VirtualBase;
  66   UINTN                         Length;
  67   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  68 } ARM_MEMORY_REGION_DESCRIPTOR;
  69
  70 typedef VOID (*CACHE_OPERATION)(VOID);
  71 typedef VOID (*LINE_OPERATION)(UINTN);
  72
  73 typedef enum {
  74   ARM_PROCESSOR_MODE_USER       = 0x10,
  75   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  76   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  77   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  78   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  79   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  80   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  81   ARM_PROCESSOR_MODE_MASK       = 0x1F
  82 } ARM_PROCESSOR_MODE;
  83
  84 #define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
  85 #define GET_CORE_ID(MpId)     ((MpId) & 0x3)
  86 #define GET_CLUSTER_ID(MpId)  (((MpId) >> 8) & 0x3C)
  87 // Get the position of the core for the Stack Offset (4 Core per Cluster)
  88 //   Position = (ClusterId * 4) + CoreId
  89 #define GET_CORE_POS(MpId)    ((((MpId) >> 6) & 0x3C) + ((MpId) & 0x3))
  90 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & 0x3)
  91
  92 ARM_CACHE_TYPE
  93 EFIAPI
  94 ArmCacheType (
  95   VOID
  96   );
  97
  98 ARM_CACHE_ARCHITECTURE
  99 EFIAPI
 100 ArmCacheArchitecture (
 101   VOID
 102   );
 103
 104 VOID
 105 EFIAPI
 106 ArmCacheInformation (
 107   OUT ARM_CACHE_INFO  *CacheInfo
 108   );
 109
 110 BOOLEAN
 111 EFIAPI
 112 ArmDataCachePresent (
 113   VOID
 114   );
 115
 116 UINTN
 117 EFIAPI
 118 ArmDataCacheSize (
 119   VOID
 120   );
 121
 122 UINTN
 123 EFIAPI
 124 ArmDataCacheAssociativity (
 125   VOID
 126   );
 127
 128 UINTN
 129 EFIAPI
 130 ArmDataCacheLineLength (
 131   VOID
 132   );
 133
 134 BOOLEAN
 135 EFIAPI
 136 ArmInstructionCachePresent (
 137   VOID
 138   );
 139
 140 UINTN
 141 EFIAPI
 142 ArmInstructionCacheSize (
 143   VOID
 144   );
 145
 146 UINTN
 147 EFIAPI
 148 ArmInstructionCacheAssociativity (
 149   VOID
 150   );
 151
 152 UINTN
 153 EFIAPI
 154 ArmInstructionCacheLineLength (
 155   VOID
 156   );
 157
 158 UINT32
 159 EFIAPI
 160 Cp15IdCode (
 161   VOID
 162   );
 163
 164 UINT32
 165 EFIAPI
 166 Cp15CacheInfo (
 167   VOID
 168   );
 169
 170 BOOLEAN
 171 EFIAPI
 172 ArmIsMpCore (
 173   VOID
 174   );
 175
 176 VOID
 177 EFIAPI
 178 ArmInvalidateDataCache (
 179   VOID
 180   );
 181
 182
 183 VOID
 184 EFIAPI
 185 ArmCleanInvalidateDataCache (
 186   VOID
 187   );
 188
 189 VOID
 190 EFIAPI
 191 ArmCleanDataCache (
 192   VOID
 193   );
 194
 195 VOID
 196 EFIAPI
 197 ArmCleanDataCacheToPoU (
 198   VOID
 199   );
 200
 201 VOID
 202 EFIAPI
 203 ArmInvalidateInstructionCache (
 204   VOID
 205   );
 206
 207 VOID
 208 EFIAPI
 209 ArmInvalidateDataCacheEntryByMVA (
 210   IN  UINTN   Address
 211   );
 212
 213 VOID
 214 EFIAPI
 215 ArmCleanDataCacheEntryByMVA (
 216   IN  UINTN   Address
 217   );
 218
 219 VOID
 220 EFIAPI
 221 ArmCleanInvalidateDataCacheEntryByMVA (
 222   IN  UINTN   Address
 223   );
 224
 225 VOID
 226 EFIAPI
 227 ArmEnableDataCache (
 228   VOID
 229   );
 230
 231 VOID
 232 EFIAPI
 233 ArmDisableDataCache (
 234   VOID
 235   );
 236
 237 VOID
 238 EFIAPI
 239 ArmEnableInstructionCache (
 240   VOID
 241   );
 242
 243 VOID
 244 EFIAPI
 245 ArmDisableInstructionCache (
 246   VOID
 247   );
 248
 249 VOID
 250 EFIAPI
 251 ArmEnableMmu (
 252   VOID
 253   );
 254
 255 VOID
 256 EFIAPI
 257 ArmDisableMmu (
 258   VOID
 259   );
 260
 261 VOID
 262 EFIAPI
 263 ArmDisableCachesAndMmu (
 264   VOID
 265   );
 266
 267 VOID
 268 EFIAPI
 269 ArmInvalidateInstructionAndDataTlb (
 270   VOID
 271   );
 272
 273 VOID
 274 EFIAPI
 275 ArmEnableInterrupts (
 276   VOID
 277   );
 278
 279 UINTN
 280 EFIAPI
 281 ArmDisableInterrupts (
 282   VOID
 283   );
 284
 285 BOOLEAN
 286 EFIAPI
 287 ArmGetInterruptState (
 288   VOID
 289   );
 290
 291 VOID
 292 EFIAPI
 293 ArmEnableFiq (
 294   VOID
 295   );
 296
 297 UINTN
 298 EFIAPI
 299 ArmDisableFiq (
 300   VOID
 301   );
 302
 303 BOOLEAN
 304 EFIAPI
 305 ArmGetFiqState (
 306   VOID
 307   );
 308
 309 VOID
 310 EFIAPI
 311 ArmInvalidateTlb (
 312   VOID
 313   );
 314
 315 VOID
 316 EFIAPI
 317 ArmUpdateTranslationTableEntry (
 318   IN  VOID     *TranslationTableEntry,
 319   IN  VOID     *Mva
 320   );
 321
 322 VOID
 323 EFIAPI
 324 ArmSetDomainAccessControl (
 325   IN  UINT32  Domain
 326   );
 327
 328 VOID
 329 EFIAPI
 330 ArmSetTTBR0 (
 331   IN  VOID  *TranslationTableBase
 332   );
 333
 334 VOID *
 335 EFIAPI
 336 ArmGetTTBR0BaseAddress (
 337   VOID
 338   );
 339
 340 VOID
 341 EFIAPI
 342 ArmConfigureMmu (
 343   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 344   OUT VOID                          **TranslationTableBase OPTIONAL,
 345   OUT UINTN                         *TranslationTableSize  OPTIONAL
 346   );
 347
 348 BOOLEAN
 349 EFIAPI
 350 ArmMmuEnabled (
 351   VOID
 352   );
 353
 354 VOID
 355 EFIAPI
 356 ArmSwitchProcessorMode (
 357   IN ARM_PROCESSOR_MODE Mode
 358   );
 359
 360 ARM_PROCESSOR_MODE
 361 EFIAPI
 362 ArmProcessorMode (
 363   VOID
 364   );
 365
 366 VOID
 367 EFIAPI
 368 ArmEnableBranchPrediction (
 369   VOID
 370   );
 371
 372 VOID
 373 EFIAPI
 374 ArmDisableBranchPrediction (
 375   VOID
 376   );
 377
 378 VOID
 379 EFIAPI
 380 ArmSetLowVectors (
 381   VOID
 382   );
 383
 384 VOID
 385 EFIAPI
 386 ArmSetHighVectors (
 387   VOID
 388   );
 389
 390 VOID
 391 EFIAPI
 392 ArmDataMemoryBarrier (
 393   VOID
 394   );
 395
 396 VOID
 397 EFIAPI
 398 ArmDataSyncronizationBarrier (
 399   VOID
 400   );
 401
 402 VOID
 403 EFIAPI
 404 ArmInstructionSynchronizationBarrier (
 405   VOID
 406   );
 407
 408 VOID
 409 EFIAPI
 410 ArmWriteVBar (
 411   IN  UINT32   VectorBase
 412   );
 413
 414 UINT32
 415 EFIAPI
 416 ArmReadVBar (
 417   VOID
 418   );
 419
 420 VOID
 421 EFIAPI
 422 ArmWriteAuxCr (
 423   IN  UINT32    Bit
 424   );
 425
 426 UINT32
 427 EFIAPI
 428 ArmReadAuxCr (
 429   VOID
 430   );
 431
 432 VOID
 433 EFIAPI
 434 ArmSetAuxCrBit (
 435   IN  UINT32    Bits
 436   );
 437
 438 VOID
 439 EFIAPI
 440 ArmCallWFI (
 441   VOID
 442   );
 443
 444 UINTN
 445 EFIAPI
 446 ArmReadMpidr (
 447   VOID
 448   );
 449
 450 VOID
 451 EFIAPI
 452 ArmWriteCPACR (
 453   IN  UINT32   Access
 454   );
 455
 456 VOID
 457 EFIAPI
 458 ArmEnableVFP (
 459   VOID
 460   );
 461
 462 VOID
 463 EFIAPI
 464 ArmWriteNsacr (
 465   IN  UINT32   SetWayFormat
 466   );
 467
 468 VOID
 469 EFIAPI
 470 ArmWriteScr (
 471   IN  UINT32   SetWayFormat
 472   );
 473
 474 VOID
 475 EFIAPI
 476 ArmWriteVMBar (
 477   IN  UINT32   VectorMonitorBase
 478   );
 479
 480 #endif // __ARM_LIB__