3 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 #include <Uefi/UefiBaseType.h>
22 #include <Chipset/ArmV7.h>
23 #elif defined(MDE_CPU_AARCH64)
24 #include <Chipset/AArch64.h>
26 #error "Unknown chipset."
30 ARM_CACHE_TYPE_WRITE_BACK
,
31 ARM_CACHE_TYPE_UNKNOWN
35 ARM_CACHE_ARCHITECTURE_UNIFIED
,
36 ARM_CACHE_ARCHITECTURE_SEPARATE
,
37 ARM_CACHE_ARCHITECTURE_UNKNOWN
38 } ARM_CACHE_ARCHITECTURE
;
42 ARM_CACHE_ARCHITECTURE Architecture
;
43 BOOLEAN DataCachePresent
;
45 UINTN DataCacheAssociativity
;
46 UINTN DataCacheLineLength
;
47 BOOLEAN InstructionCachePresent
;
48 UINTN InstructionCacheSize
;
49 UINTN InstructionCacheAssociativity
;
50 UINTN InstructionCacheLineLength
;
54 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
56 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
57 * be used in Secure World to distinguished Secure to Non-Secure memory.
60 ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
= 0,
61 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
,
62 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
,
63 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
,
64 ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
,
65 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
,
66 ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
,
67 ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
68 } ARM_MEMORY_REGION_ATTRIBUTES
;
70 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
73 EFI_PHYSICAL_ADDRESS PhysicalBase
;
74 EFI_VIRTUAL_ADDRESS VirtualBase
;
76 ARM_MEMORY_REGION_ATTRIBUTES Attributes
;
77 } ARM_MEMORY_REGION_DESCRIPTOR
;
79 typedef VOID (*CACHE_OPERATION
)(VOID
);
80 typedef VOID (*LINE_OPERATION
)(UINTN
);
86 ARM_PROCESSOR_MODE_USER
= 0x10,
87 ARM_PROCESSOR_MODE_FIQ
= 0x11,
88 ARM_PROCESSOR_MODE_IRQ
= 0x12,
89 ARM_PROCESSOR_MODE_SUPERVISOR
= 0x13,
90 ARM_PROCESSOR_MODE_ABORT
= 0x17,
91 ARM_PROCESSOR_MODE_HYP
= 0x1A,
92 ARM_PROCESSOR_MODE_UNDEFINED
= 0x1B,
93 ARM_PROCESSOR_MODE_SYSTEM
= 0x1F,
94 ARM_PROCESSOR_MODE_MASK
= 0x1F
100 #define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
101 #define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
102 #define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
103 #define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
104 #define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
105 #define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
107 #define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
108 #define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
109 #define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
110 #define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
111 #define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
112 #define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
117 #define ARM_CORE_AFF0 0xFF
118 #define ARM_CORE_AFF1 (0xFF << 8)
119 #define ARM_CORE_AFF2 (0xFF << 16)
120 #define ARM_CORE_AFF3 (0xFFULL << 32)
122 #define ARM_CORE_MASK ARM_CORE_AFF0
123 #define ARM_CLUSTER_MASK ARM_CORE_AFF1
124 #define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
125 #define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
126 #define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
127 #define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
135 ARM_CACHE_ARCHITECTURE
137 ArmCacheArchitecture (
143 ArmCacheInformation (
144 OUT ARM_CACHE_INFO
*CacheInfo
149 ArmDataCachePresent (
161 ArmDataCacheAssociativity (
167 ArmDataCacheLineLength (
173 ArmInstructionCachePresent (
179 ArmInstructionCacheSize (
185 ArmInstructionCacheAssociativity (
191 ArmInstructionCacheLineLength (
197 ArmIsArchTimerImplemented (
227 ArmInvalidateDataCache (
234 ArmCleanInvalidateDataCache (
246 ArmCleanDataCacheToPoU (
252 ArmInvalidateInstructionCache (
258 ArmInvalidateDataCacheEntryByMVA (
264 ArmCleanDataCacheEntryByMVA (
270 ArmCleanInvalidateDataCacheEntryByMVA (
276 ArmInvalidateDataCacheEntryBySetWay (
277 IN UINTN SetWayFormat
282 ArmCleanDataCacheEntryBySetWay (
283 IN UINTN SetWayFormat
288 ArmCleanInvalidateDataCacheEntryBySetWay (
289 IN UINTN SetWayFormat
300 ArmDisableDataCache (
306 ArmEnableInstructionCache (
312 ArmDisableInstructionCache (
330 ArmEnableCachesAndMmu (
336 ArmDisableCachesAndMmu (
342 ArmEnableInterrupts (
348 ArmDisableInterrupts (
354 ArmGetInterruptState (
360 ArmEnableAsynchronousAbort (
366 ArmDisableAsynchronousAbort (
401 * Invalidate Data and Instruction TLBs
411 ArmUpdateTranslationTableEntry (
412 IN VOID
*TranslationTableEntry
,
418 ArmSetDomainAccessControl (
425 IN VOID
*TranslationTableBase
430 ArmGetTTBR0BaseAddress (
437 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
438 OUT VOID
**TranslationTableBase OPTIONAL
,
439 OUT UINTN
*TranslationTableSize OPTIONAL
450 ArmEnableBranchPrediction (
456 ArmDisableBranchPrediction (
474 ArmDrainWriteBuffer (
480 ArmDataMemoryBarrier (
486 ArmDataSynchronizationBarrier (
492 ArmInstructionSynchronizationBarrier (
582 Get the Secure Configuration Register value
584 @return Value read from the Secure Configuration Register
594 Set the Secure Configuration Register
596 @param Value Value to write to the Secure Configuration Register
614 IN UINT32 VectorMonitorBase
632 IN UINTN HypModeVectorBase
637 // Helper functions for accessing CPU ACTLR
660 ArmUnsetCpuActlrBit (
665 ArmSetMemoryRegionNoExec (
666 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
671 ArmClearMemoryRegionNoExec (
672 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
677 ArmSetMemoryRegionReadOnly (
678 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
683 ArmClearMemoryRegionReadOnly (
684 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
688 #endif // __ARM_LIB__