ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #ifdef ARM_CPU_ARMv6
  23     #include <Chipset/ARM1176JZ-S.h>
  24   #else
  25     #include <Chipset/ArmV7.h>
  26   #endif
  27 #elif defined(MDE_CPU_AARCH64)
  28   #include <Chipset/AArch64.h>
  29 #else
  30  #error "Unknown chipset."
  31 #endif
  32
  33 typedef enum {
  34   ARM_CACHE_TYPE_WRITE_BACK,
  35   ARM_CACHE_TYPE_UNKNOWN
  36 } ARM_CACHE_TYPE;
  37
  38 typedef enum {
  39   ARM_CACHE_ARCHITECTURE_UNIFIED,
  40   ARM_CACHE_ARCHITECTURE_SEPARATE,
  41   ARM_CACHE_ARCHITECTURE_UNKNOWN
  42 } ARM_CACHE_ARCHITECTURE;
  43
  44 typedef struct {
  45   ARM_CACHE_TYPE          Type;
  46   ARM_CACHE_ARCHITECTURE  Architecture;
  47   BOOLEAN                 DataCachePresent;
  48   UINTN                   DataCacheSize;
  49   UINTN                   DataCacheAssociativity;
  50   UINTN                   DataCacheLineLength;
  51   BOOLEAN                 InstructionCachePresent;
  52   UINTN                   InstructionCacheSize;
  53   UINTN                   InstructionCacheAssociativity;
  54   UINTN                   InstructionCacheLineLength;
  55 } ARM_CACHE_INFO;
  56
  57 /**
  58  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  59  *
  60  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  61  * be used in Secure World to distinguished Secure to Non-Secure memory.
  62  */
  63 typedef enum {
  64   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  66   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  67   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  68   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  69   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  70   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  71   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  72 } ARM_MEMORY_REGION_ATTRIBUTES;
  73
  74 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  75
  76 typedef struct {
  77   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  78   EFI_VIRTUAL_ADDRESS           VirtualBase;
  79   UINT64                        Length;
  80   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  81 } ARM_MEMORY_REGION_DESCRIPTOR;
  82
  83 typedef VOID (*CACHE_OPERATION)(VOID);
  84 typedef VOID (*LINE_OPERATION)(UINTN);
  85
  86 //
  87 // ARM Processor Mode
  88 //
  89 typedef enum {
  90   ARM_PROCESSOR_MODE_USER       = 0x10,
  91   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  92   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  93   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  94   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  95   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  96   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  97   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  98   ARM_PROCESSOR_MODE_MASK       = 0x1F
  99 } ARM_PROCESSOR_MODE;
 100
 101 //
 102 // ARM Cpu IDs
 103 //
 104 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
 105 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
 106 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
 107 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
 108 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
 109 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
 110
 111 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
 112 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
 113 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
 114 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
 115 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
 116 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
 117
 118 //
 119 // ARM MP Core IDs
 120 //
 121 #define ARM_CORE_MASK         0xFF
 122 #define ARM_CLUSTER_MASK      (0xFF << 8)
 123 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 124 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 125 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 126 // Get the position of the core for the Stack Offset (4 Core per Cluster)
 127 //   Position = (ClusterId * 4) + CoreId
 128 #define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
 129 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 130
 131 ARM_CACHE_TYPE
 132 EFIAPI
 133 ArmCacheType (
 134   VOID
 135   );
 136
 137 ARM_CACHE_ARCHITECTURE
 138 EFIAPI
 139 ArmCacheArchitecture (
 140   VOID
 141   );
 142
 143 VOID
 144 EFIAPI
 145 ArmCacheInformation (
 146   OUT ARM_CACHE_INFO  *CacheInfo
 147   );
 148
 149 BOOLEAN
 150 EFIAPI
 151 ArmDataCachePresent (
 152   VOID
 153   );
 154
 155 UINTN
 156 EFIAPI
 157 ArmDataCacheSize (
 158   VOID
 159   );
 160
 161 UINTN
 162 EFIAPI
 163 ArmDataCacheAssociativity (
 164   VOID
 165   );
 166
 167 UINTN
 168 EFIAPI
 169 ArmDataCacheLineLength (
 170   VOID
 171   );
 172
 173 BOOLEAN
 174 EFIAPI
 175 ArmInstructionCachePresent (
 176   VOID
 177   );
 178
 179 UINTN
 180 EFIAPI
 181 ArmInstructionCacheSize (
 182   VOID
 183   );
 184
 185 UINTN
 186 EFIAPI
 187 ArmInstructionCacheAssociativity (
 188   VOID
 189   );
 190
 191 UINTN
 192 EFIAPI
 193 ArmInstructionCacheLineLength (
 194   VOID
 195   );
 196
 197 UINTN
 198 EFIAPI
 199 ArmIsArchTimerImplemented (
 200   VOID
 201   );
 202
 203 UINTN
 204 EFIAPI
 205 ArmReadIdPfr0 (
 206   VOID
 207   );
 208
 209 UINTN
 210 EFIAPI
 211 ArmReadIdPfr1 (
 212   VOID
 213   );
 214
 215 UINT32
 216 EFIAPI
 217 Cp15CacheInfo (
 218   VOID
 219   );
 220
 221 BOOLEAN
 222 EFIAPI
 223 ArmIsMpCore (
 224   VOID
 225   );
 226
 227 VOID
 228 EFIAPI
 229 ArmInvalidateDataCache (
 230   VOID
 231   );
 232
 233
 234 VOID
 235 EFIAPI
 236 ArmCleanInvalidateDataCache (
 237   VOID
 238   );
 239
 240 VOID
 241 EFIAPI
 242 ArmCleanDataCache (
 243   VOID
 244   );
 245
 246 VOID
 247 EFIAPI
 248 ArmCleanDataCacheToPoU (
 249   VOID
 250   );
 251
 252 VOID
 253 EFIAPI
 254 ArmInvalidateInstructionCache (
 255   VOID
 256   );
 257
 258 VOID
 259 EFIAPI
 260 ArmInvalidateDataCacheEntryByMVA (
 261   IN  UINTN   Address
 262   );
 263
 264 VOID
 265 EFIAPI
 266 ArmCleanDataCacheEntryByMVA (
 267   IN  UINTN   Address
 268   );
 269
 270 VOID
 271 EFIAPI
 272 ArmCleanInvalidateDataCacheEntryByMVA (
 273   IN  UINTN   Address
 274   );
 275
 276 VOID
 277 EFIAPI
 278 ArmInvalidateDataCacheEntryBySetWay (
 279   IN  UINTN  SetWayFormat
 280   );
 281
 282 VOID
 283 EFIAPI
 284 ArmCleanDataCacheEntryBySetWay (
 285   IN  UINTN  SetWayFormat
 286   );
 287
 288 VOID
 289 EFIAPI
 290 ArmCleanInvalidateDataCacheEntryBySetWay (
 291   IN  UINTN   SetWayFormat
 292   );
 293
 294 VOID
 295 EFIAPI
 296 ArmEnableDataCache (
 297   VOID
 298   );
 299
 300 VOID
 301 EFIAPI
 302 ArmDisableDataCache (
 303   VOID
 304   );
 305
 306 VOID
 307 EFIAPI
 308 ArmEnableInstructionCache (
 309   VOID
 310   );
 311
 312 VOID
 313 EFIAPI
 314 ArmDisableInstructionCache (
 315   VOID
 316   );
 317
 318 VOID
 319 EFIAPI
 320 ArmEnableMmu (
 321   VOID
 322   );
 323
 324 VOID
 325 EFIAPI
 326 ArmDisableMmu (
 327   VOID
 328   );
 329
 330 VOID
 331 EFIAPI
 332 ArmEnableCachesAndMmu (
 333   VOID
 334   );
 335
 336 VOID
 337 EFIAPI
 338 ArmDisableCachesAndMmu (
 339   VOID
 340   );
 341
 342 VOID
 343 EFIAPI
 344 ArmInvalidateInstructionAndDataTlb (
 345   VOID
 346   );
 347
 348 VOID
 349 EFIAPI
 350 ArmEnableInterrupts (
 351   VOID
 352   );
 353
 354 UINTN
 355 EFIAPI
 356 ArmDisableInterrupts (
 357   VOID
 358   );
 359
 360 BOOLEAN
 361 EFIAPI
 362 ArmGetInterruptState (
 363   VOID
 364   );
 365
 366 VOID
 367 EFIAPI
 368 ArmEnableAsynchronousAbort (
 369   VOID
 370   );
 371
 372 UINTN
 373 EFIAPI
 374 ArmDisableAsynchronousAbort (
 375   VOID
 376   );
 377
 378 VOID
 379 EFIAPI
 380 ArmEnableIrq (
 381   VOID
 382   );
 383
 384 UINTN
 385 EFIAPI
 386 ArmDisableIrq (
 387   VOID
 388   );
 389
 390 VOID
 391 EFIAPI
 392 ArmEnableFiq (
 393   VOID
 394   );
 395
 396 UINTN
 397 EFIAPI
 398 ArmDisableFiq (
 399   VOID
 400   );
 401
 402 BOOLEAN
 403 EFIAPI
 404 ArmGetFiqState (
 405   VOID
 406   );
 407
 408 VOID
 409 EFIAPI
 410 ArmInvalidateTlb (
 411   VOID
 412   );
 413
 414 VOID
 415 EFIAPI
 416 ArmUpdateTranslationTableEntry (
 417   IN  VOID     *TranslationTableEntry,
 418   IN  VOID     *Mva
 419   );
 420
 421 VOID
 422 EFIAPI
 423 ArmSetDomainAccessControl (
 424   IN  UINT32  Domain
 425   );
 426
 427 VOID
 428 EFIAPI
 429 ArmSetTTBR0 (
 430   IN  VOID  *TranslationTableBase
 431   );
 432
 433 VOID *
 434 EFIAPI
 435 ArmGetTTBR0BaseAddress (
 436   VOID
 437   );
 438
 439 RETURN_STATUS
 440 EFIAPI
 441 ArmConfigureMmu (
 442   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 443   OUT VOID                         **TranslationTableBase OPTIONAL,
 444   OUT UINTN                         *TranslationTableSize  OPTIONAL
 445   );
 446
 447 BOOLEAN
 448 EFIAPI
 449 ArmMmuEnabled (
 450   VOID
 451   );
 452
 453 VOID
 454 EFIAPI
 455 ArmEnableBranchPrediction (
 456   VOID
 457   );
 458
 459 VOID
 460 EFIAPI
 461 ArmDisableBranchPrediction (
 462   VOID
 463   );
 464
 465 VOID
 466 EFIAPI
 467 ArmSetLowVectors (
 468   VOID
 469   );
 470
 471 VOID
 472 EFIAPI
 473 ArmSetHighVectors (
 474   VOID
 475   );
 476
 477 VOID
 478 EFIAPI
 479 ArmDrainWriteBuffer (
 480   VOID
 481   );
 482
 483 VOID
 484 EFIAPI
 485 ArmDataMemoryBarrier (
 486   VOID
 487   );
 488
 489 VOID
 490 EFIAPI
 491 ArmDataSyncronizationBarrier (
 492   VOID
 493   );
 494
 495 VOID
 496 EFIAPI
 497 ArmInstructionSynchronizationBarrier (
 498   VOID
 499   );
 500
 501 VOID
 502 EFIAPI
 503 ArmWriteVBar (
 504   IN  UINTN   VectorBase
 505   );
 506
 507 UINTN
 508 EFIAPI
 509 ArmReadVBar (
 510   VOID
 511   );
 512
 513 VOID
 514 EFIAPI
 515 ArmWriteAuxCr (
 516   IN  UINT32    Bit
 517   );
 518
 519 UINT32
 520 EFIAPI
 521 ArmReadAuxCr (
 522   VOID
 523   );
 524
 525 VOID
 526 EFIAPI
 527 ArmSetAuxCrBit (
 528   IN  UINT32    Bits
 529   );
 530
 531 VOID
 532 EFIAPI
 533 ArmUnsetAuxCrBit (
 534   IN  UINT32    Bits
 535   );
 536
 537 VOID
 538 EFIAPI
 539 ArmCallSEV (
 540   VOID
 541   );
 542
 543 VOID
 544 EFIAPI
 545 ArmCallWFE (
 546   VOID
 547   );
 548
 549 VOID
 550 EFIAPI
 551 ArmCallWFI (
 552
 553   VOID
 554   );
 555
 556 UINTN
 557 EFIAPI
 558 ArmReadMpidr (
 559   VOID
 560   );
 561
 562 UINTN
 563 EFIAPI
 564 ArmReadMidr (
 565   VOID
 566   );
 567
 568 UINT32
 569 EFIAPI
 570 ArmReadCpacr (
 571   VOID
 572   );
 573
 574 VOID
 575 EFIAPI
 576 ArmWriteCpacr (
 577   IN  UINT32   Access
 578   );
 579
 580 VOID
 581 EFIAPI
 582 ArmEnableVFP (
 583   VOID
 584   );
 585
 586 UINT32
 587 EFIAPI
 588 ArmReadScr (
 589   VOID
 590   );
 591
 592 VOID
 593 EFIAPI
 594 ArmWriteScr (
 595   IN  UINT32   SetWayFormat
 596   );
 597
 598 UINT32
 599 EFIAPI
 600 ArmReadMVBar (
 601   VOID
 602   );
 603
 604 VOID
 605 EFIAPI
 606 ArmWriteMVBar (
 607   IN  UINT32   VectorMonitorBase
 608   );
 609
 610 UINT32
 611 EFIAPI
 612 ArmReadSctlr (
 613   VOID
 614   );
 615
 616 UINTN
 617 EFIAPI
 618 ArmReadHVBar (
 619   VOID
 620   );
 621
 622 VOID
 623 EFIAPI
 624 ArmWriteHVBar (
 625   IN  UINTN   HypModeVectorBase
 626   );
 627
 628 #endif // __ARM_LIB__