ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #ifdef ARM_CPU_ARMv6
  23     #include <Chipset/ARM1176JZ-S.h>
  24   #else
  25     #include <Chipset/ArmV7.h>
  26   #endif
  27 #elif defined(MDE_CPU_AARCH64)
  28   #include <Chipset/AArch64.h>
  29 #else
  30  #error "Unknown chipset."
  31 #endif
  32
  33 typedef enum {
  34   ARM_CACHE_TYPE_WRITE_BACK,
  35   ARM_CACHE_TYPE_UNKNOWN
  36 } ARM_CACHE_TYPE;
  37
  38 typedef enum {
  39   ARM_CACHE_ARCHITECTURE_UNIFIED,
  40   ARM_CACHE_ARCHITECTURE_SEPARATE,
  41   ARM_CACHE_ARCHITECTURE_UNKNOWN
  42 } ARM_CACHE_ARCHITECTURE;
  43
  44 typedef struct {
  45   ARM_CACHE_TYPE          Type;
  46   ARM_CACHE_ARCHITECTURE  Architecture;
  47   BOOLEAN                 DataCachePresent;
  48   UINTN                   DataCacheSize;
  49   UINTN                   DataCacheAssociativity;
  50   UINTN                   DataCacheLineLength;
  51   BOOLEAN                 InstructionCachePresent;
  52   UINTN                   InstructionCacheSize;
  53   UINTN                   InstructionCacheAssociativity;
  54   UINTN                   InstructionCacheLineLength;
  55 } ARM_CACHE_INFO;
  56
  57 /**
  58  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  59  *
  60  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  61  * be used in Secure World to distinguished Secure to Non-Secure memory.
  62  */
  63 typedef enum {
  64   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  66   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  67   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  68   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  69   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  70   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  71   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  72 } ARM_MEMORY_REGION_ATTRIBUTES;
  73
  74 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  75
  76 typedef struct {
  77   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  78   EFI_VIRTUAL_ADDRESS           VirtualBase;
  79   UINT64                        Length;
  80   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  81 } ARM_MEMORY_REGION_DESCRIPTOR;
  82
  83 typedef VOID (*CACHE_OPERATION)(VOID);
  84 typedef VOID (*LINE_OPERATION)(UINTN);
  85
  86 //
  87 // ARM Processor Mode
  88 //
  89 typedef enum {
  90   ARM_PROCESSOR_MODE_USER       = 0x10,
  91   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  92   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  93   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  94   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  95   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  96   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  97   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  98   ARM_PROCESSOR_MODE_MASK       = 0x1F
  99 } ARM_PROCESSOR_MODE;
 100
 101 //
 102 // ARM Cpu IDs
 103 //
 104 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
 105 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
 106 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
 107 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
 108 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
 109 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
 110
 111 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
 112 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
 113 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
 114 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
 115 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
 116 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
 117
 118 //
 119 // ARM MP Core IDs
 120 //
 121 #define ARM_CORE_MASK         0xFF
 122 #define ARM_CLUSTER_MASK      (0xFF << 8)
 123 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 124 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 125 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 126 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 127
 128 ARM_CACHE_TYPE
 129 EFIAPI
 130 ArmCacheType (
 131   VOID
 132   );
 133
 134 ARM_CACHE_ARCHITECTURE
 135 EFIAPI
 136 ArmCacheArchitecture (
 137   VOID
 138   );
 139
 140 VOID
 141 EFIAPI
 142 ArmCacheInformation (
 143   OUT ARM_CACHE_INFO  *CacheInfo
 144   );
 145
 146 BOOLEAN
 147 EFIAPI
 148 ArmDataCachePresent (
 149   VOID
 150   );
 151
 152 UINTN
 153 EFIAPI
 154 ArmDataCacheSize (
 155   VOID
 156   );
 157
 158 UINTN
 159 EFIAPI
 160 ArmDataCacheAssociativity (
 161   VOID
 162   );
 163
 164 UINTN
 165 EFIAPI
 166 ArmDataCacheLineLength (
 167   VOID
 168   );
 169
 170 BOOLEAN
 171 EFIAPI
 172 ArmInstructionCachePresent (
 173   VOID
 174   );
 175
 176 UINTN
 177 EFIAPI
 178 ArmInstructionCacheSize (
 179   VOID
 180   );
 181
 182 UINTN
 183 EFIAPI
 184 ArmInstructionCacheAssociativity (
 185   VOID
 186   );
 187
 188 UINTN
 189 EFIAPI
 190 ArmInstructionCacheLineLength (
 191   VOID
 192   );
 193
 194 UINTN
 195 EFIAPI
 196 ArmIsArchTimerImplemented (
 197   VOID
 198   );
 199
 200 UINTN
 201 EFIAPI
 202 ArmReadIdPfr0 (
 203   VOID
 204   );
 205
 206 UINTN
 207 EFIAPI
 208 ArmReadIdPfr1 (
 209   VOID
 210   );
 211
 212 UINTN
 213 EFIAPI
 214 ArmCacheInfo (
 215   VOID
 216   );
 217
 218 BOOLEAN
 219 EFIAPI
 220 ArmIsMpCore (
 221   VOID
 222   );
 223
 224 VOID
 225 EFIAPI
 226 ArmInvalidateDataCache (
 227   VOID
 228   );
 229
 230
 231 VOID
 232 EFIAPI
 233 ArmCleanInvalidateDataCache (
 234   VOID
 235   );
 236
 237 VOID
 238 EFIAPI
 239 ArmCleanDataCache (
 240   VOID
 241   );
 242
 243 VOID
 244 EFIAPI
 245 ArmCleanDataCacheToPoU (
 246   VOID
 247   );
 248
 249 VOID
 250 EFIAPI
 251 ArmInvalidateInstructionCache (
 252   VOID
 253   );
 254
 255 VOID
 256 EFIAPI
 257 ArmInvalidateDataCacheEntryByMVA (
 258   IN  UINTN   Address
 259   );
 260
 261 VOID
 262 EFIAPI
 263 ArmCleanDataCacheEntryByMVA (
 264   IN  UINTN   Address
 265   );
 266
 267 VOID
 268 EFIAPI
 269 ArmCleanInvalidateDataCacheEntryByMVA (
 270   IN  UINTN   Address
 271   );
 272
 273 VOID
 274 EFIAPI
 275 ArmInvalidateDataCacheEntryBySetWay (
 276   IN  UINTN  SetWayFormat
 277   );
 278
 279 VOID
 280 EFIAPI
 281 ArmCleanDataCacheEntryBySetWay (
 282   IN  UINTN  SetWayFormat
 283   );
 284
 285 VOID
 286 EFIAPI
 287 ArmCleanInvalidateDataCacheEntryBySetWay (
 288   IN  UINTN   SetWayFormat
 289   );
 290
 291 VOID
 292 EFIAPI
 293 ArmEnableDataCache (
 294   VOID
 295   );
 296
 297 VOID
 298 EFIAPI
 299 ArmDisableDataCache (
 300   VOID
 301   );
 302
 303 VOID
 304 EFIAPI
 305 ArmEnableInstructionCache (
 306   VOID
 307   );
 308
 309 VOID
 310 EFIAPI
 311 ArmDisableInstructionCache (
 312   VOID
 313   );
 314
 315 VOID
 316 EFIAPI
 317 ArmEnableMmu (
 318   VOID
 319   );
 320
 321 VOID
 322 EFIAPI
 323 ArmDisableMmu (
 324   VOID
 325   );
 326
 327 VOID
 328 EFIAPI
 329 ArmEnableCachesAndMmu (
 330   VOID
 331   );
 332
 333 VOID
 334 EFIAPI
 335 ArmDisableCachesAndMmu (
 336   VOID
 337   );
 338
 339 VOID
 340 EFIAPI
 341 ArmInvalidateInstructionAndDataTlb (
 342   VOID
 343   );
 344
 345 VOID
 346 EFIAPI
 347 ArmEnableInterrupts (
 348   VOID
 349   );
 350
 351 UINTN
 352 EFIAPI
 353 ArmDisableInterrupts (
 354   VOID
 355   );
 356
 357 BOOLEAN
 358 EFIAPI
 359 ArmGetInterruptState (
 360   VOID
 361   );
 362
 363 VOID
 364 EFIAPI
 365 ArmEnableAsynchronousAbort (
 366   VOID
 367   );
 368
 369 UINTN
 370 EFIAPI
 371 ArmDisableAsynchronousAbort (
 372   VOID
 373   );
 374
 375 VOID
 376 EFIAPI
 377 ArmEnableIrq (
 378   VOID
 379   );
 380
 381 UINTN
 382 EFIAPI
 383 ArmDisableIrq (
 384   VOID
 385   );
 386
 387 VOID
 388 EFIAPI
 389 ArmEnableFiq (
 390   VOID
 391   );
 392
 393 UINTN
 394 EFIAPI
 395 ArmDisableFiq (
 396   VOID
 397   );
 398
 399 BOOLEAN
 400 EFIAPI
 401 ArmGetFiqState (
 402   VOID
 403   );
 404
 405 VOID
 406 EFIAPI
 407 ArmInvalidateTlb (
 408   VOID
 409   );
 410
 411 VOID
 412 EFIAPI
 413 ArmUpdateTranslationTableEntry (
 414   IN  VOID     *TranslationTableEntry,
 415   IN  VOID     *Mva
 416   );
 417
 418 VOID
 419 EFIAPI
 420 ArmSetDomainAccessControl (
 421   IN  UINT32  Domain
 422   );
 423
 424 VOID
 425 EFIAPI
 426 ArmSetTTBR0 (
 427   IN  VOID  *TranslationTableBase
 428   );
 429
 430 VOID *
 431 EFIAPI
 432 ArmGetTTBR0BaseAddress (
 433   VOID
 434   );
 435
 436 RETURN_STATUS
 437 EFIAPI
 438 ArmConfigureMmu (
 439   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 440   OUT VOID                         **TranslationTableBase OPTIONAL,
 441   OUT UINTN                         *TranslationTableSize  OPTIONAL
 442   );
 443
 444 BOOLEAN
 445 EFIAPI
 446 ArmMmuEnabled (
 447   VOID
 448   );
 449
 450 VOID
 451 EFIAPI
 452 ArmEnableBranchPrediction (
 453   VOID
 454   );
 455
 456 VOID
 457 EFIAPI
 458 ArmDisableBranchPrediction (
 459   VOID
 460   );
 461
 462 VOID
 463 EFIAPI
 464 ArmSetLowVectors (
 465   VOID
 466   );
 467
 468 VOID
 469 EFIAPI
 470 ArmSetHighVectors (
 471   VOID
 472   );
 473
 474 VOID
 475 EFIAPI
 476 ArmDrainWriteBuffer (
 477   VOID
 478   );
 479
 480 VOID
 481 EFIAPI
 482 ArmDataMemoryBarrier (
 483   VOID
 484   );
 485
 486 VOID
 487 EFIAPI
 488 ArmDataSyncronizationBarrier (
 489   VOID
 490   );
 491
 492 VOID
 493 EFIAPI
 494 ArmInstructionSynchronizationBarrier (
 495   VOID
 496   );
 497
 498 VOID
 499 EFIAPI
 500 ArmWriteVBar (
 501   IN  UINTN   VectorBase
 502   );
 503
 504 UINTN
 505 EFIAPI
 506 ArmReadVBar (
 507   VOID
 508   );
 509
 510 VOID
 511 EFIAPI
 512 ArmWriteAuxCr (
 513   IN  UINT32    Bit
 514   );
 515
 516 UINT32
 517 EFIAPI
 518 ArmReadAuxCr (
 519   VOID
 520   );
 521
 522 VOID
 523 EFIAPI
 524 ArmSetAuxCrBit (
 525   IN  UINT32    Bits
 526   );
 527
 528 VOID
 529 EFIAPI
 530 ArmUnsetAuxCrBit (
 531   IN  UINT32    Bits
 532   );
 533
 534 VOID
 535 EFIAPI
 536 ArmCallSEV (
 537   VOID
 538   );
 539
 540 VOID
 541 EFIAPI
 542 ArmCallWFE (
 543   VOID
 544   );
 545
 546 VOID
 547 EFIAPI
 548 ArmCallWFI (
 549
 550   VOID
 551   );
 552
 553 UINTN
 554 EFIAPI
 555 ArmReadMpidr (
 556   VOID
 557   );
 558
 559 UINTN
 560 EFIAPI
 561 ArmReadMidr (
 562   VOID
 563   );
 564
 565 UINT32
 566 EFIAPI
 567 ArmReadCpacr (
 568   VOID
 569   );
 570
 571 VOID
 572 EFIAPI
 573 ArmWriteCpacr (
 574   IN  UINT32   Access
 575   );
 576
 577 VOID
 578 EFIAPI
 579 ArmEnableVFP (
 580   VOID
 581   );
 582
 583 UINT32
 584 EFIAPI
 585 ArmReadScr (
 586   VOID
 587   );
 588
 589 VOID
 590 EFIAPI
 591 ArmWriteScr (
 592   IN  UINT32   SetWayFormat
 593   );
 594
 595 UINT32
 596 EFIAPI
 597 ArmReadMVBar (
 598   VOID
 599   );
 600
 601 VOID
 602 EFIAPI
 603 ArmWriteMVBar (
 604   IN  UINT32   VectorMonitorBase
 605   );
 606
 607 UINT32
 608 EFIAPI
 609 ArmReadSctlr (
 610   VOID
 611   );
 612
 613 UINTN
 614 EFIAPI
 615 ArmReadHVBar (
 616   VOID
 617   );
 618
 619 VOID
 620 EFIAPI
 621 ArmWriteHVBar (
 622   IN  UINTN   HypModeVectorBase
 623   );
 624
 625
 626 //
 627 // Helper functions for accessing CPU ACTLR
 628 //
 629
 630 UINTN
 631 EFIAPI
 632 ArmReadCpuActlr (
 633   VOID
 634   );
 635
 636 VOID
 637 EFIAPI
 638 ArmWriteCpuActlr (
 639   IN  UINTN Val
 640   );
 641
 642 VOID
 643 EFIAPI
 644 ArmSetCpuActlrBit (
 645   IN  UINTN    Bits
 646   );
 647
 648 VOID
 649 EFIAPI
 650 ArmUnsetCpuActlrBit (
 651   IN  UINTN    Bits
 652   );
 653
 654 #endif // __ARM_LIB__