ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #include <Chipset/ArmV7.h>
  23 #elif defined(MDE_CPU_AARCH64)
  24   #include <Chipset/AArch64.h>
  25 #else
  26  #error "Unknown chipset."
  27 #endif
  28
  29 /**
  30  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  31  *
  32  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  33  * be used in Secure World to distinguished Secure to Non-Secure memory.
  34  */
  35 typedef enum {
  36   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  37   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  38   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  39   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  40   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  41   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  42   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  43   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  44 } ARM_MEMORY_REGION_ATTRIBUTES;
  45
  46 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  47
  48 typedef struct {
  49   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  50   EFI_VIRTUAL_ADDRESS           VirtualBase;
  51   UINT64                        Length;
  52   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  53 } ARM_MEMORY_REGION_DESCRIPTOR;
  54
  55 typedef VOID (*CACHE_OPERATION)(VOID);
  56 typedef VOID (*LINE_OPERATION)(UINTN);
  57
  58 //
  59 // ARM Processor Mode
  60 //
  61 typedef enum {
  62   ARM_PROCESSOR_MODE_USER       = 0x10,
  63   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  64   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  65   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  66   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  67   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  68   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  69   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  70   ARM_PROCESSOR_MODE_MASK       = 0x1F
  71 } ARM_PROCESSOR_MODE;
  72
  73 //
  74 // ARM Cpu IDs
  75 //
  76 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
  77 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
  78 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
  79 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
  80 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
  81 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
  82
  83 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
  84 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
  85 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
  86 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
  87 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
  88 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
  89
  90 //
  91 // ARM MP Core IDs
  92 //
  93 #define ARM_CORE_AFF0         0xFF
  94 #define ARM_CORE_AFF1         (0xFF << 8)
  95 #define ARM_CORE_AFF2         (0xFF << 16)
  96 #define ARM_CORE_AFF3         (0xFFULL << 32)
  97
  98 #define ARM_CORE_MASK         ARM_CORE_AFF0
  99 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 100 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 101 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 102 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 103 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 104
 105 UINTN
 106 EFIAPI
 107 ArmDataCacheLineLength (
 108   VOID
 109   );
 110
 111 UINTN
 112 EFIAPI
 113 ArmInstructionCacheLineLength (
 114   VOID
 115   );
 116
 117 UINTN
 118 EFIAPI
 119 ArmIsArchTimerImplemented (
 120   VOID
 121   );
 122
 123 UINTN
 124 EFIAPI
 125 ArmReadIdPfr0 (
 126   VOID
 127   );
 128
 129 UINTN
 130 EFIAPI
 131 ArmReadIdPfr1 (
 132   VOID
 133   );
 134
 135 UINTN
 136 EFIAPI
 137 ArmCacheInfo (
 138   VOID
 139   );
 140
 141 BOOLEAN
 142 EFIAPI
 143 ArmIsMpCore (
 144   VOID
 145   );
 146
 147 VOID
 148 EFIAPI
 149 ArmInvalidateDataCache (
 150   VOID
 151   );
 152
 153
 154 VOID
 155 EFIAPI
 156 ArmCleanInvalidateDataCache (
 157   VOID
 158   );
 159
 160 VOID
 161 EFIAPI
 162 ArmCleanDataCache (
 163   VOID
 164   );
 165
 166 VOID
 167 EFIAPI
 168 ArmInvalidateInstructionCache (
 169   VOID
 170   );
 171
 172 VOID
 173 EFIAPI
 174 ArmInvalidateDataCacheEntryByMVA (
 175   IN  UINTN   Address
 176   );
 177
 178 VOID
 179 EFIAPI
 180 ArmCleanDataCacheEntryByMVA (
 181   IN  UINTN   Address
 182   );
 183
 184 VOID
 185 EFIAPI
 186 ArmCleanInvalidateDataCacheEntryByMVA (
 187   IN  UINTN   Address
 188   );
 189
 190 VOID
 191 EFIAPI
 192 ArmInvalidateDataCacheEntryBySetWay (
 193   IN  UINTN  SetWayFormat
 194   );
 195
 196 VOID
 197 EFIAPI
 198 ArmCleanDataCacheEntryBySetWay (
 199   IN  UINTN  SetWayFormat
 200   );
 201
 202 VOID
 203 EFIAPI
 204 ArmCleanInvalidateDataCacheEntryBySetWay (
 205   IN  UINTN   SetWayFormat
 206   );
 207
 208 VOID
 209 EFIAPI
 210 ArmEnableDataCache (
 211   VOID
 212   );
 213
 214 VOID
 215 EFIAPI
 216 ArmDisableDataCache (
 217   VOID
 218   );
 219
 220 VOID
 221 EFIAPI
 222 ArmEnableInstructionCache (
 223   VOID
 224   );
 225
 226 VOID
 227 EFIAPI
 228 ArmDisableInstructionCache (
 229   VOID
 230   );
 231
 232 VOID
 233 EFIAPI
 234 ArmEnableMmu (
 235   VOID
 236   );
 237
 238 VOID
 239 EFIAPI
 240 ArmDisableMmu (
 241   VOID
 242   );
 243
 244 VOID
 245 EFIAPI
 246 ArmEnableCachesAndMmu (
 247   VOID
 248   );
 249
 250 VOID
 251 EFIAPI
 252 ArmDisableCachesAndMmu (
 253   VOID
 254   );
 255
 256 VOID
 257 EFIAPI
 258 ArmEnableInterrupts (
 259   VOID
 260   );
 261
 262 UINTN
 263 EFIAPI
 264 ArmDisableInterrupts (
 265   VOID
 266   );
 267
 268 BOOLEAN
 269 EFIAPI
 270 ArmGetInterruptState (
 271   VOID
 272   );
 273
 274 VOID
 275 EFIAPI
 276 ArmEnableAsynchronousAbort (
 277   VOID
 278   );
 279
 280 UINTN
 281 EFIAPI
 282 ArmDisableAsynchronousAbort (
 283   VOID
 284   );
 285
 286 VOID
 287 EFIAPI
 288 ArmEnableIrq (
 289   VOID
 290   );
 291
 292 UINTN
 293 EFIAPI
 294 ArmDisableIrq (
 295   VOID
 296   );
 297
 298 VOID
 299 EFIAPI
 300 ArmEnableFiq (
 301   VOID
 302   );
 303
 304 UINTN
 305 EFIAPI
 306 ArmDisableFiq (
 307   VOID
 308   );
 309
 310 BOOLEAN
 311 EFIAPI
 312 ArmGetFiqState (
 313   VOID
 314   );
 315
 316 /**
 317  * Invalidate Data and Instruction TLBs
 318  */
 319 VOID
 320 EFIAPI
 321 ArmInvalidateTlb (
 322   VOID
 323   );
 324
 325 VOID
 326 EFIAPI
 327 ArmUpdateTranslationTableEntry (
 328   IN  VOID     *TranslationTableEntry,
 329   IN  VOID     *Mva
 330   );
 331
 332 VOID
 333 EFIAPI
 334 ArmSetDomainAccessControl (
 335   IN  UINT32  Domain
 336   );
 337
 338 VOID
 339 EFIAPI
 340 ArmSetTTBR0 (
 341   IN  VOID  *TranslationTableBase
 342   );
 343
 344 VOID *
 345 EFIAPI
 346 ArmGetTTBR0BaseAddress (
 347   VOID
 348   );
 349
 350 RETURN_STATUS
 351 EFIAPI
 352 ArmConfigureMmu (
 353   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 354   OUT VOID                         **TranslationTableBase OPTIONAL,
 355   OUT UINTN                         *TranslationTableSize  OPTIONAL
 356   );
 357
 358 BOOLEAN
 359 EFIAPI
 360 ArmMmuEnabled (
 361   VOID
 362   );
 363
 364 VOID
 365 EFIAPI
 366 ArmEnableBranchPrediction (
 367   VOID
 368   );
 369
 370 VOID
 371 EFIAPI
 372 ArmDisableBranchPrediction (
 373   VOID
 374   );
 375
 376 VOID
 377 EFIAPI
 378 ArmSetLowVectors (
 379   VOID
 380   );
 381
 382 VOID
 383 EFIAPI
 384 ArmSetHighVectors (
 385   VOID
 386   );
 387
 388 VOID
 389 EFIAPI
 390 ArmDrainWriteBuffer (
 391   VOID
 392   );
 393
 394 VOID
 395 EFIAPI
 396 ArmDataMemoryBarrier (
 397   VOID
 398   );
 399
 400 VOID
 401 EFIAPI
 402 ArmDataSynchronizationBarrier (
 403   VOID
 404   );
 405
 406 VOID
 407 EFIAPI
 408 ArmInstructionSynchronizationBarrier (
 409   VOID
 410   );
 411
 412 VOID
 413 EFIAPI
 414 ArmWriteVBar (
 415   IN  UINTN   VectorBase
 416   );
 417
 418 UINTN
 419 EFIAPI
 420 ArmReadVBar (
 421   VOID
 422   );
 423
 424 VOID
 425 EFIAPI
 426 ArmWriteAuxCr (
 427   IN  UINT32    Bit
 428   );
 429
 430 UINT32
 431 EFIAPI
 432 ArmReadAuxCr (
 433   VOID
 434   );
 435
 436 VOID
 437 EFIAPI
 438 ArmSetAuxCrBit (
 439   IN  UINT32    Bits
 440   );
 441
 442 VOID
 443 EFIAPI
 444 ArmUnsetAuxCrBit (
 445   IN  UINT32    Bits
 446   );
 447
 448 VOID
 449 EFIAPI
 450 ArmCallSEV (
 451   VOID
 452   );
 453
 454 VOID
 455 EFIAPI
 456 ArmCallWFE (
 457   VOID
 458   );
 459
 460 VOID
 461 EFIAPI
 462 ArmCallWFI (
 463
 464   VOID
 465   );
 466
 467 UINTN
 468 EFIAPI
 469 ArmReadMpidr (
 470   VOID
 471   );
 472
 473 UINTN
 474 EFIAPI
 475 ArmReadMidr (
 476   VOID
 477   );
 478
 479 UINT32
 480 EFIAPI
 481 ArmReadCpacr (
 482   VOID
 483   );
 484
 485 VOID
 486 EFIAPI
 487 ArmWriteCpacr (
 488   IN  UINT32   Access
 489   );
 490
 491 VOID
 492 EFIAPI
 493 ArmEnableVFP (
 494   VOID
 495   );
 496
 497 /**
 498   Get the Secure Configuration Register value
 499
 500   @return   Value read from the Secure Configuration Register
 501
 502 **/
 503 UINT32
 504 EFIAPI
 505 ArmReadScr (
 506   VOID
 507   );
 508
 509 /**
 510   Set the Secure Configuration Register
 511
 512   @param Value   Value to write to the Secure Configuration Register
 513
 514 **/
 515 VOID
 516 EFIAPI
 517 ArmWriteScr (
 518   IN  UINT32   Value
 519   );
 520
 521 UINT32
 522 EFIAPI
 523 ArmReadMVBar (
 524   VOID
 525   );
 526
 527 VOID
 528 EFIAPI
 529 ArmWriteMVBar (
 530   IN  UINT32   VectorMonitorBase
 531   );
 532
 533 UINT32
 534 EFIAPI
 535 ArmReadSctlr (
 536   VOID
 537   );
 538
 539 UINTN
 540 EFIAPI
 541 ArmReadHVBar (
 542   VOID
 543   );
 544
 545 VOID
 546 EFIAPI
 547 ArmWriteHVBar (
 548   IN  UINTN   HypModeVectorBase
 549   );
 550
 551
 552 //
 553 // Helper functions for accessing CPU ACTLR
 554 //
 555
 556 UINTN
 557 EFIAPI
 558 ArmReadCpuActlr (
 559   VOID
 560   );
 561
 562 VOID
 563 EFIAPI
 564 ArmWriteCpuActlr (
 565   IN  UINTN Val
 566   );
 567
 568 VOID
 569 EFIAPI
 570 ArmSetCpuActlrBit (
 571   IN  UINTN    Bits
 572   );
 573
 574 VOID
 575 EFIAPI
 576 ArmUnsetCpuActlrBit (
 577   IN  UINTN    Bits
 578   );
 579
 580 RETURN_STATUS
 581 ArmSetMemoryRegionNoExec (
 582   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 583   IN  UINT64                    Length
 584   );
 585
 586 RETURN_STATUS
 587 ArmClearMemoryRegionNoExec (
 588   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 589   IN  UINT64                    Length
 590   );
 591
 592 RETURN_STATUS
 593 ArmSetMemoryRegionReadOnly (
 594   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 595   IN  UINT64                    Length
 596   );
 597
 598 RETURN_STATUS
 599 ArmClearMemoryRegionReadOnly (
 600   IN  EFI_PHYSICAL_ADDRESS      BaseAddress,
 601   IN  UINT64                    Length
 602   );
 603
 604 #endif // __ARM_LIB__