ArmPkg/Include/Library/L2X0CacheLib.h

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #ifndef L2CACHELIB_H_
  16 #define L2CACHELIB_H_
  17
  18 #define L2_LATENCY                          7
  19
  20 #define L2_TAG_ACCESS_LATENCY               L2_LATENCY
  21 #define L2_TAG_SETUP_LATENCY                L2_LATENCY
  22 #define L2_DATA_ACCESS_LATENCY              L2_LATENCY
  23 #define L2_DATA_SETUP_LATENCY               L2_LATENCY
  24
  25
  26 #define L2X0_CACHEID            0x000
  27 #define L2X0_CTRL               0x100
  28 #define L2X0_AUXCTRL            0x104
  29 #define L230_TAG_LATENCY        0x108
  30 #define L230_DATA_LATENCY       0x10C
  31 #define L2X0_INTCLEAR           0x220
  32 #define L2X0_CACHE_SYNC                 0x730
  33 #define L2X0_INVWAY             0x77C
  34 #define L2X0_CLEAN_WAY          0x7BC
  35 #define L2X0_PFCTRL             0xF60
  36 #define L2X0_PWRCTRL            0xF80
  37
  38 #define L2X0_CACHEID_IMPLEMENTER_ARM        0x41
  39 #define L2X0_CACHEID_PARTNUM_PL310          0x03
  40
  41 #define L2X0_CTRL_ENABLED                   0x1
  42 #define L2X0_CTRL_DISABLED                  0x0
  43
  44 #define L2X0_AUXCTRL_EXCLUSIVE              (1<<12)
  45 #define L2X0_AUXCTRL_WAYSIZE_16KB           (0x001 << 17)
  46 #define L2X0_AUXCTRL_WAYSIZE_32KB           (0x010 << 17)
  47 #define L2X0_AUXCTRL_WAYSIZE_64KB           (0x011 << 17)
  48 #define L2X0_AUXCTRL_WAYSIZE_128KB          (0x100 << 17)
  49 #define L2X0_AUXCTRL_WAYSIZE_256KB          (0x101 << 17)
  50 #define L2X0_AUXCTRL_WAYSIZE_512KB          (0x110 << 17)
  51 #define L2X0_AUXCTRL_EM                     (1 << 20)
  52 #define L2x0_AUXCTRL_AW_AWCACHE             (0x00 << 23)
  53 #define L2x0_AUXCTRL_AW_NOALLOC             (0x01 << 23)
  54 #define L2x0_AUXCTRL_AW_OVERRIDE            (0x10 << 23)
  55 #define L2X0_AUXCTRL_SBO                    (1 << 25)
  56 #define L2X0_AUXCTRL_NSAC                   (1 << 27)
  57 #define L2x0_AUXCTRL_DPREFETCH              (1 << 28)
  58 #define L2x0_AUXCTRL_IPREFETCH              (1 << 29)
  59
  60 VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled);
  61
  62 #endif /* L2CACHELIB_H_ */