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[mirror_edk2.git] / ArmPkg / Library / ArmDisassemblerLib / ThumbDisassembler.c
1 /** @file
2 Default exception handler
3
4 Copyright (c) 2008-2010, Apple Inc. All rights reserved.
5
6 All rights reserved. This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include <Base.h>
17 #include <Library/BaseLib.h>
18 #include <Library/PrintLib.h>
19
20 extern CHAR8 *gCondition[];
21
22 extern CHAR8 *gReg[];
23
24 #define LOAD_STORE_FORMAT1 1
25 #define LOAD_STORE_FORMAT2 2
26 #define LOAD_STORE_FORMAT3 3
27 #define LOAD_STORE_FORMAT4 4
28 #define LOAD_STORE_MULTIPLE_FORMAT1 5
29 #define PUSH_FORMAT 6
30 #define POP_FORMAT 106
31 #define IMMED_8 7
32 #define CONDITIONAL_BRANCH 8
33 #define UNCONDITIONAL_BRANCH 9
34 #define UNCONDITIONAL_BRANCH_SHORT 109
35 #define BRANCH_EXCHANGE 10
36 #define DATA_FORMAT1 11
37 #define DATA_FORMAT2 12
38 #define DATA_FORMAT3 13
39 #define DATA_FORMAT4 14
40 #define DATA_FORMAT5 15
41 #define DATA_FORMAT6_SP 16
42 #define DATA_FORMAT6_PC 116
43 #define DATA_FORMAT7 17
44 #define DATA_FORMAT8 19
45 #define CPS_FORMAT 20
46 #define ENDIAN_FORMAT 21
47
48 #define B_T3 200
49 #define B_T4 201
50 #define BL_T2 202
51
52
53 typedef struct {
54 CHAR8 *Start;
55 UINT32 OpCode;
56 UINT32 Mask;
57 UINT32 AddressMode;
58 } THUMB_INSTRUCTIONS;
59
60 THUMB_INSTRUCTIONS gOpThumb[] = {
61 // Thumb 16-bit instrucitons
62 // Op Mask Format
63 { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 },
64
65 { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
66 { "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
67 { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
68 { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
69 { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
70 { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
71 { "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },
72
73 { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
74
75 { "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },
76 { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },
77
78 { "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },
79 { "B" , 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },
80 { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },
81 { "BX" , 0x4700, 0xff87, BRANCH_EXCHANGE },
82
83 { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },
84 { "BKPT", 0xdf00, 0xff00, IMMED_8 },
85 { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },
86
87 { "CMP" , 0x2800, 0xf800, DATA_FORMAT3 },
88 { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },
89 { "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },
90
91 { "CPS" , 0xb660, 0xffe8, CPS_FORMAT },
92 { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
93 { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
94
95 { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
96 { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 },
97 { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
98 { "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
99 { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 },
100 { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1 },
101 { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 },
102 { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1 },
103 { "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
104 { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 },
105 { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
106
107 { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
108 { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
109 { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
110 { "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
111 { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
112
113 { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
114 { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
115 { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
116
117 { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
118 { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
119 { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
120 { "ORR" , 0x4180, 0xffc0, DATA_FORMAT5 },
121 { "POP" , 0xbc00, 0xfe00, POP_FORMAT },
122 { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
123
124 { "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },
125 { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },
126 { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },
127
128 { "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },
129 { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
130 { "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
131
132 { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
133 { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 },
134 { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 },
135 { "STR" , 0x4000, 0xf800, LOAD_STORE_FORMAT3 },
136 { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 },
137 { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1 },
138 { "STRB" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 },
139 { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1 },
140 { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 },
141
142 { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
143 { "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
144 { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
145 { "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
146
147 { "SWI" , 0xdf00, 0xff00, IMMED_8 },
148 { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
149 { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
150 { "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
151 { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
152 { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 }
153 };
154
155 THUMB_INSTRUCTIONS gOpThumb2[] = {
156 { "B", 0xf0008000, 0xf800d000, B_T3 },
157 { "B", 0xf0009000, 0xf800d000, B_T4 },
158 { "BL", 0xf000d000, 0xf800d000, B_T4 },
159 { "BLX", 0xf000c000, 0xf800d000, BL_T2 }
160
161 #if 0
162
163 // 32-bit Thumb instructions op1 01
164
165 // 1110 100x x0xx xxxx xxxx xxxx xxxx xxxx Load/store multiple
166 { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
167 { "SRS" , 0xe98dc000, 0xffdffff0, SRS_IA_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
168 { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
169 { "RFE" , 0xe990c000, 0xffd0ffff, RFE_IA_FORMAT }, // RFE{IA}<c> <Rn>{!}
170
171 { "STM" , 0xe8800000, 0xffd00000, STM_FORMAT }, // STM<c>.W <Rn>{!},<registers>
172 { "LDM" , 0xe8900000, 0xffd00000, STM_FORMAT }, // LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
173 { "POP" , 0xe8bd0000, 0xffff2000, REGLIST_FORMAT }, // POP<c>.W <registers> >1 register
174 { "POP" , 0xf85d0b04, 0xffff0fff, RT_FORMAT }, // POP<c>.W <registers> 1 register
175
176 { "STMDB", 0xe9000000, 0xffd00000, STM_FORMAT }, // STMDB
177 { "PUSH" , 0xe8bd0000, 0xffffa000, REGLIST_FORMAT }, // PUSH<c>.W <registers> >1 register
178 { "PUSH" , 0xf84d0b04, 0xffff0fff, RT_FORMAT }, // PUSH<c>.W <registers> 1 register
179 { "LDMDB", 0xe9102000, 0xffd02000, STM_FORMAT }, // LDMDB<c> <Rn>{!},<registers>
180
181 // 1110 100x x1xx xxxx xxxx xxxx xxxx xxxx Load/store dual,
182 { "STREX" , 0xe0400000, 0xfff000f0, 3REG_IMM8_FORMAT }, // STREX<c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
183 { "STREXB", 0xe8c00f40, 0xfff00ff0, 3REG_FORMAT }, // STREXB<c> <Rd>,<Rt>,[<Rn>]
184 { "STREXD", 0xe8c00070, 0xfff000f0, 4REG_FORMAT }, // STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]
185 { "STREXH", 0xe8c00f70, 0xfff00ff0, 3REG_FORMAT }, // STREXH<c> <Rd>,<Rt>,[<Rn>]
186 { "STRH", 0xf8c00000, 0xfff00000, 2REG_IMM8_FORMAT }, // STRH<c>.W <Rt>,[<Rn>{,#<imm12>}]
187 { "STRH", 0xf8200000, 0xfff00000, }, // STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]
188
189
190
191 // 1110 101x xxxx xxxx xxxx xxxx xxxx xxxx Data-processing
192 // 1110 11xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
193
194 // 1111 0x0x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing modified immediate
195 // 1111 0x1x xxxx xxxx 0xxx xxxx xxxx xxxx Data-processing plain immediate
196 // 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx Branches
197
198 // 1111 1000 xxx0 xxxx xxxx xxxx xxxx xxxx Store single data item
199 // 1111 1001 xxx0 xxxx xxxx xxxx xxxx xxxx SIMD or load/store
200 // 1111 100x x001 xxxx xxxx xxxx xxxx xxxx Load byte, memory hints
201 // 1111 100x x011 xxxx xxxx xxxx xxxx xxxx Load halfword, memory hints
202 // 1111 100x x101 xxxx xxxx xxxx xxxx xxxx Load word
203
204 // 1111 1 010 xxxx xxxx xxxx xxxx xxxx xxxx Data-processing register
205 // 1111 1 011 0xxx xxxx xxxx xxxx xxxx xxxx Multiply
206 // 1111 1 011 1xxx xxxx xxxx xxxx xxxx xxxx Long Multiply
207 // 1111 1 1xx xxxx xxxx xxxx xxxx xxxx xxxx Coprocessor
208 #endif
209 };
210
211 CHAR8 mThumbMregListStr[4*15 + 1];
212
213 CHAR8 *
214 ThumbMRegList (
215 UINT32 RegBitMask
216 )
217 {
218 UINTN Index, Start, End;
219 CHAR8 *Str;
220 BOOLEAN First;
221
222 Str = mThumbMregListStr;
223 *Str = '\0';
224 AsciiStrCat (Str, "{");
225 // R0 - R7, PC
226 for (Index = 0, First = TRUE; Index <= 15; Index++) {
227 if ((RegBitMask & (1 << Index)) != 0) {
228 Start = End = Index;
229 for (Index++; ((RegBitMask & (1 << Index)) != 0) && (Index <= 9); Index++) {
230 End = Index;
231 }
232
233 if (!First) {
234 AsciiStrCat (Str, ",");
235 } else {
236 First = FALSE;
237 }
238
239 if (Start == End) {
240 AsciiStrCat (Str, gReg[Start]);
241 } else {
242 AsciiStrCat (Str, gReg[Start]);
243 AsciiStrCat (Str, "-");
244 AsciiStrCat (Str, gReg[End]);
245 }
246 }
247 }
248 if (First) {
249 AsciiStrCat (Str, "ERROR");
250 }
251 AsciiStrCat (Str, "}");
252
253 // BugBug: Make caller pass in buffer it is cleaner
254 return mThumbMregListStr;
255 }
256
257 UINT32
258 SignExtend32 (
259 IN UINT32 Data,
260 IN UINT32 TopBit
261 )
262 {
263 if (((Data & TopBit) == 0) || (TopBit == BIT31)) {
264 return Data;
265 }
266
267 do {
268 TopBit <<= 1;
269 Data |= TopBit;
270 } while ((TopBit & BIT31) != BIT31);
271
272 return Data;
273 }
274
275 /**
276 Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
277 point to next instructin.
278
279 We cheat and only decode instructions that access
280 memory. If the instruction is not found we dump the instruction in hex.
281
282 @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
283 @param Buf Buffer to sprintf disassembly into.
284 @param Size Size of Buf in bytes.
285 @param Extended TRUE dump hex for instruction too.
286
287 **/
288 VOID
289 DisassembleThumbInstruction (
290 IN UINT16 **OpCodePtrPtr,
291 OUT CHAR8 *Buf,
292 OUT UINTN Size,
293 IN BOOLEAN Extended
294 )
295 {
296 UINT16 *OpCodePtr;
297 UINT16 OpCode;
298 UINT32 OpCode32;
299 UINT32 Index;
300 UINT32 Offset;
301 UINT16 Rd, Rn, Rm;
302 BOOLEAN H1, H2, imod;
303 UINT32 PC, Target;
304 CHAR8 *Cond;
305 BOOLEAN S, J1, J2;
306
307 OpCodePtr = *OpCodePtrPtr;
308 OpCode = **OpCodePtrPtr;
309
310 // Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
311 OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);
312
313 // These register names match branch form, but not others
314 Rd = OpCode & 0x7;
315 Rn = (OpCode >> 3) & 0x7;
316 Rm = (OpCode >> 6) & 0x7;
317 H1 = (OpCode & BIT7) != 0;
318 H2 = (OpCode & BIT6) != 0;
319 imod = (OpCode & BIT4) != 0;
320 PC = (UINT32)(UINTN)OpCodePtr;
321
322 // Increment by the minimum instruction size, Thumb2 could be bigger
323 *OpCodePtrPtr += 1;
324
325 for (Index = 0; Index < sizeof (gOpThumb)/sizeof (THUMB_INSTRUCTIONS); Index++) {
326 if ((OpCode & gOpThumb[Index].Mask) == gOpThumb[Index].OpCode) {
327 if (Extended) {
328 Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode, gOpThumb[Index].Start);
329 } else {
330 Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
331 }
332 switch (gOpThumb[Index].AddressMode) {
333 case LOAD_STORE_FORMAT1:
334 // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
335 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
336 return;
337 case LOAD_STORE_FORMAT2:
338 // A6.5.1 <Rd>, [<Rn>, <Rm>]
339 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
340 return;
341 case LOAD_STORE_FORMAT3:
342 // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
343 Target = (OpCode & 0xff) << 2;
344 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PC + 4 + Target);
345 return;
346 case LOAD_STORE_FORMAT4:
347 // Rt, [SP, #imm8]
348 Target = (OpCode & 0xff) << 2;
349 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target, PC + 3 + Target);
350 return;
351
352 case LOAD_STORE_MULTIPLE_FORMAT1:
353 // <Rn>!, {r0-r7}
354 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
355 return;
356
357 case POP_FORMAT:
358 // POP {r0-r7,pc}
359 AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
360 return;
361
362 case PUSH_FORMAT:
363 // PUSH {r0-r7,lr}
364 AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
365 return;
366
367
368 case IMMED_8:
369 // A6.7 <immed_8>
370 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
371 return;
372
373 case CONDITIONAL_BRANCH:
374 // A6.3.1 B<cond> <target_address>
375 // Patch in the condition code. A little hack but based on "%-6a"
376 Cond = gCondition[(OpCode >> 8) & 0xf];
377 Buf[Offset-5] = *Cond++;
378 Buf[Offset-4] = *Cond;
379 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
380 return;
381 case UNCONDITIONAL_BRANCH_SHORT:
382 // A6.3.2 B <target_address>
383 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
384 return;
385
386 case BRANCH_EXCHANGE:
387 // A6.3.3 BX|BLX <Rm>
388 AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);
389 return;
390
391 case DATA_FORMAT1:
392 // A6.4.3 <Rd>, <Rn>, <Rm>
393 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
394 return;
395 case DATA_FORMAT2:
396 // A6.4.3 <Rd>, <Rn>, #3_bit_immed
397 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
398 return;
399 case DATA_FORMAT3:
400 // A6.4.3 <Rd>|<Rn>, #imm8
401 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
402 return;
403 case DATA_FORMAT4:
404 // A6.4.3 <Rd>|<Rm>, #immed_5
405 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
406 return;
407 case DATA_FORMAT5:
408 // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
409 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
410 return;
411 case DATA_FORMAT6_SP:
412 // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
413 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
414 return;
415 case DATA_FORMAT6_PC:
416 // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
417 AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
418 return;
419 case DATA_FORMAT7:
420 // A6.4.3 SP, SP, #<7_Bit_immed>
421 AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
422 return;
423 case DATA_FORMAT8:
424 // A6.4.3 <Rd>|<Rn>, <Rm>
425 AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);
426 return;
427
428 case CPS_FORMAT:
429 // A7.1.24
430 AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
431 return;
432
433 case ENDIAN_FORMAT:
434 // A7.1.24
435 AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
436 return;
437 }
438 }
439 }
440
441
442 // Thumb2 are 32-bit instructions
443 *OpCodePtrPtr += 1;
444 for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
445 if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
446 if (Extended) {
447 Offset = AsciiSPrint (Buf, Size, "0x%04x %-6a", OpCode32, gOpThumb2[Index].Start);
448 } else {
449 Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);
450 }
451 switch (gOpThumb2[Index].AddressMode) {
452 case B_T3:
453 Cond = gCondition[(OpCode32 >> 22) & 0xf];
454 Buf[Offset-5] = *Cond++;
455 Buf[Offset-4] = *Cond;
456 // S:J2:J1:imm6:imm11:0
457 Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);
458 Target |= (OpCode & BIT11) ? BIT18 : 0; // J2
459 Target |= (OpCode & BIT13) ? BIT17 : 0; // J1
460 Target |= (OpCode & BIT26) ? BIT19 : 0; // S
461 Target = SignExtend32 (Target, BIT19);
462 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Target);
463 return;
464 case B_T4:
465 // S:I1:I2:imm10:imm11:0
466 Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
467 S = (OpCode & BIT26);
468 J1 = (OpCode & BIT13);
469 J2 = (OpCode & BIT11);
470 Target |= !(J2 ^ S) ? BIT21 : 0; // I2
471 Target |= !(J1 ^ S) ? BIT22 : 0; // I1
472 Target |= (OpCode & BIT26) ? BIT23 : 0; // S
473 Target = SignExtend32 (Target, BIT23);
474 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Target);
475 return;
476
477 case BL_T2:
478 // S:I1:I2:imm10:imm11:0
479 Target = ((OpCode32 << 2) & 0x1ffc) + ((OpCode32 >> 3) & 0x7fe000);
480 S = (OpCode & BIT26);
481 J1 = (OpCode & BIT13);
482 J2 = (OpCode & BIT11);
483 Target |= !(J2 ^ S) ? BIT22 : 0; // I2
484 Target |= !(J1 ^ S) ? BIT23 : 0; // I1
485 Target |= (OpCode & BIT26) ? BIT24 : 0; // S
486 Target = SignExtend32 (Target, BIT24);
487 AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Target);
488 return;
489 }
490 }
491 }
492
493 AsciiSPrint (Buf, Size, "0x%08x", OpCode32);
494 }
495
496
497
498 VOID
499 DisassembleArmInstruction (
500 IN UINT32 **OpCodePtr,
501 OUT CHAR8 *Buf,
502 OUT UINTN Size,
503 IN BOOLEAN Extended
504 );
505
506
507 /**
508 Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to
509 point to next instructin.
510
511 We cheat and only decode instructions that access
512 memory. If the instruction is not found we dump the instruction in hex.
513
514 @param OpCodePtrPtr Pointer to pointer of ARM Thumb instruction to disassemble.
515 @param Thumb TRUE for Thumb(2), FALSE for ARM instruction stream
516 @param Extended TRUE dump hex for instruction too.
517 @param Buf Buffer to sprintf disassembly into.
518 @param Size Size of Buf in bytes.
519
520 **/
521 VOID
522 DisassembleInstruction (
523 IN UINT8 **OpCodePtr,
524 IN BOOLEAN Thumb,
525 IN BOOLEAN Extended,
526 OUT CHAR8 *Buf,
527 OUT UINTN Size
528 )
529 {
530 if (Thumb) {
531 DisassembleThumbInstruction ((UINT16 **)OpCodePtr, Buf, Size, Extended);
532 } else {
533 DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
534 }
535 }
536
EFI Development Kit II mirror for PVE