ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <Chipset/AArch64.h>
  17 #include <AsmMacroIoLibV8.h>
  18
  19 .text
  20 .align 3
  21
  22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  26 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  27 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  28 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  29 GCC_ASM_EXPORT (ArmEnableMmu)
  30 GCC_ASM_EXPORT (ArmDisableMmu)
  31 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  32 GCC_ASM_EXPORT (ArmMmuEnabled)
  33 GCC_ASM_EXPORT (ArmEnableDataCache)
  34 GCC_ASM_EXPORT (ArmDisableDataCache)
  35 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  36 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  37 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
  38 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
  39 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  40 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  41 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
  42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  43 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmWriteVBar)
  46 GCC_ASM_EXPORT (ArmReadVBar)
  47 GCC_ASM_EXPORT (ArmEnableVFP)
  48 GCC_ASM_EXPORT (ArmCallWFI)
  49 GCC_ASM_EXPORT (ArmReadMpidr)
  50 GCC_ASM_EXPORT (ArmReadTpidrurw)
  51 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  52 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  53 GCC_ASM_EXPORT (ArmReadIdPfr0)
  54 GCC_ASM_EXPORT (ArmReadIdPfr1)
  55 GCC_ASM_EXPORT (ArmWriteHcr)
  56 GCC_ASM_EXPORT (ArmReadCurrentEL)
  57
  58 .set CTRL_M_BIT,      (1 << 0)
  59 .set CTRL_A_BIT,      (1 << 1)
  60 .set CTRL_C_BIT,      (1 << 2)
  61 .set CTRL_I_BIT,      (1 << 12)
  62 .set CTRL_V_BIT,      (1 << 12)
  63 .set CPACR_VFP_BITS,  (3 << 20)
  64
  65 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  66   dc      ivac, x0    // Invalidate single data cache line
  67   ret
  68
  69
  70 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  71   dc      cvac, x0    // Clean single data cache line
  72   ret
  73
  74
  75 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  76   dc      civac, x0   // Clean and invalidate single data cache line
  77   ret
  78
  79
  80 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  81   dc      isw, x0     // Invalidate this line
  82   ret
  83
  84
  85 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  86   dc      cisw, x0    // Clean and Invalidate this line
  87   ret
  88
  89
  90 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  91   dc      csw, x0     // Clean this line
  92   ret
  93
  94
  95 ASM_PFX(ArmInvalidateInstructionCache):
  96   ic      iallu       // Invalidate entire instruction cache
  97   dsb     sy
  98   isb
  99   ret
 100
 101
 102 ASM_PFX(ArmEnableMmu):
 103    EL1_OR_EL2_OR_EL3(x1)
 104 1: mrs     x0, sctlr_el1       // Read System control register EL1
 105    b       4f
 106 2: mrs     x0, sctlr_el2       // Read System control register EL2
 107    b       4f
 108 3: mrs     x0, sctlr_el3       // Read System control register EL3
 109 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
 110    EL1_OR_EL2_OR_EL3(x1)
 111 1: tlbi    vmalle1
 112    dsb     nsh
 113    isb
 114    msr     sctlr_el1, x0       // Write back
 115    b       4f
 116 2: tlbi    alle2
 117    dsb     nsh
 118    isb
 119    msr     sctlr_el2, x0       // Write back
 120    b       4f
 121 3: tlbi    alle3
 122    dsb     nsh
 123    isb
 124    msr     sctlr_el3, x0       // Write back
 125 4: isb
 126    ret
 127
 128
 129 ASM_PFX(ArmDisableMmu):
 130    EL1_OR_EL2_OR_EL3(x1)
 131 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
 132    b       4f
 133 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 134    b       4f
 135 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 136 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 137    EL1_OR_EL2_OR_EL3(x1)
 138 1: msr     sctlr_el1, x0        // Write back
 139    tlbi    vmalle1
 140    b       4f
 141 2: msr     sctlr_el2, x0        // Write back
 142    tlbi    alle2
 143    b       4f
 144 3: msr     sctlr_el3, x0        // Write back
 145    tlbi    alle3
 146 4: dsb     sy
 147    isb
 148    ret
 149
 150
 151 ASM_PFX(ArmDisableCachesAndMmu):
 152    EL1_OR_EL2_OR_EL3(x1)
 153 1: mrs     x0, sctlr_el1        // Get control register EL1
 154    b       4f
 155 2: mrs     x0, sctlr_el2        // Get control register EL2
 156    b       4f
 157 3: mrs     x0, sctlr_el3        // Get control register EL3
 158 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 159    and     x0, x0, x1
 160    EL1_OR_EL2_OR_EL3(x1)
 161 1: msr     sctlr_el1, x0        // Write back control register
 162    b       4f
 163 2: msr     sctlr_el2, x0        // Write back control register
 164    b       4f
 165 3: msr     sctlr_el3, x0        // Write back control register
 166 4: dsb     sy
 167    isb
 168    ret
 169
 170
 171 ASM_PFX(ArmMmuEnabled):
 172    EL1_OR_EL2_OR_EL3(x1)
 173 1: mrs     x0, sctlr_el1        // Get control register EL1
 174    b       4f
 175 2: mrs     x0, sctlr_el2        // Get control register EL2
 176    b       4f
 177 3: mrs     x0, sctlr_el3        // Get control register EL3
 178 4: and     x0, x0, #CTRL_M_BIT
 179    ret
 180
 181
 182 ASM_PFX(ArmEnableDataCache):
 183    EL1_OR_EL2_OR_EL3(x1)
 184 1: mrs     x0, sctlr_el1        // Get control register EL1
 185    b       4f
 186 2: mrs     x0, sctlr_el2        // Get control register EL2
 187    b       4f
 188 3: mrs     x0, sctlr_el3        // Get control register EL3
 189 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 190    EL1_OR_EL2_OR_EL3(x1)
 191 1: msr     sctlr_el1, x0        // Write back control register
 192    b       4f
 193 2: msr     sctlr_el2, x0        // Write back control register
 194    b       4f
 195 3: msr     sctlr_el3, x0        // Write back control register
 196 4: dsb     sy
 197    isb
 198    ret
 199
 200
 201 ASM_PFX(ArmDisableDataCache):
 202    EL1_OR_EL2_OR_EL3(x1)
 203 1: mrs     x0, sctlr_el1        // Get control register EL1
 204    b       4f
 205 2: mrs     x0, sctlr_el2        // Get control register EL2
 206    b       4f
 207 3: mrs     x0, sctlr_el3        // Get control register EL3
 208 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 209    EL1_OR_EL2_OR_EL3(x1)
 210 1: msr     sctlr_el1, x0        // Write back control register
 211    b       4f
 212 2: msr     sctlr_el2, x0        // Write back control register
 213    b       4f
 214 3: msr     sctlr_el3, x0        // Write back control register
 215 4: dsb     sy
 216    isb
 217    ret
 218
 219
 220 ASM_PFX(ArmEnableInstructionCache):
 221    EL1_OR_EL2_OR_EL3(x1)
 222 1: mrs     x0, sctlr_el1        // Get control register EL1
 223    b       4f
 224 2: mrs     x0, sctlr_el2        // Get control register EL2
 225    b       4f
 226 3: mrs     x0, sctlr_el3        // Get control register EL3
 227 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 228    EL1_OR_EL2_OR_EL3(x1)
 229 1: msr     sctlr_el1, x0        // Write back control register
 230    b       4f
 231 2: msr     sctlr_el2, x0        // Write back control register
 232    b       4f
 233 3: msr     sctlr_el3, x0        // Write back control register
 234 4: dsb     sy
 235    isb
 236    ret
 237
 238
 239 ASM_PFX(ArmDisableInstructionCache):
 240    EL1_OR_EL2_OR_EL3(x1)
 241 1: mrs     x0, sctlr_el1        // Get control register EL1
 242    b       4f
 243 2: mrs     x0, sctlr_el2        // Get control register EL2
 244    b       4f
 245 3: mrs     x0, sctlr_el3        // Get control register EL3
 246 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 247    EL1_OR_EL2_OR_EL3(x1)
 248 1: msr     sctlr_el1, x0        // Write back control register
 249    b       4f
 250 2: msr     sctlr_el2, x0        // Write back control register
 251    b       4f
 252 3: msr     sctlr_el3, x0        // Write back control register
 253 4: dsb     sy
 254    isb
 255    ret
 256
 257
 258 ASM_PFX(ArmEnableAlignmentCheck):
 259    EL1_OR_EL2(x1)
 260 1: mrs     x0, sctlr_el1        // Get control register EL1
 261    b       3f
 262 2: mrs     x0, sctlr_el2        // Get control register EL2
 263 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 264    EL1_OR_EL2(x1)
 265 1: msr     sctlr_el1, x0        // Write back control register
 266    b       3f
 267 2: msr     sctlr_el2, x0        // Write back control register
 268 3: dsb     sy
 269    isb
 270    ret
 271
 272
 273 ASM_PFX(ArmDisableAlignmentCheck):
 274    EL1_OR_EL2_OR_EL3(x1)
 275 1: mrs     x0, sctlr_el1        // Get control register EL1
 276    b       4f
 277 2: mrs     x0, sctlr_el2        // Get control register EL2
 278    b       4f
 279 3: mrs     x0, sctlr_el3        // Get control register EL3
 280 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 281    EL1_OR_EL2_OR_EL3(x1)
 282 1: msr     sctlr_el1, x0        // Write back control register
 283    b       4f
 284 2: msr     sctlr_el2, x0        // Write back control register
 285    b       4f
 286 3: msr     sctlr_el3, x0        // Write back control register
 287 4: dsb     sy
 288    isb
 289    ret
 290
 291
 292 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 293 ASM_PFX(ArmEnableBranchPrediction):
 294   ret
 295
 296
 297 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 298 ASM_PFX(ArmDisableBranchPrediction):
 299   ret
 300
 301
 302 ASM_PFX(AArch64AllDataCachesOperation):
 303 // We can use regs 0-7 and 9-15 without having to save/restore.
 304 // Save our link register on the stack. - The stack must always be quad-word aligned
 305   str   x30, [sp, #-16]!
 306   mov   x1, x0                  // Save Function call in x1
 307   mrs   x6, clidr_el1           // Read EL1 CLIDR
 308   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 309   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 310                                 // right to ease the access to CSSELR and the Set/Way operation.
 311   cbz   x3, L_Finished          // No need to clean if LoC is 0
 312   mov   x10, #0                 // Start clean at cache level 0
 313
 314 Loop1:
 315   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 316   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 317   and   x12, x12, #7            // get those 3 bits alone
 318   cmp   x12, #2                 // what cache at this level?
 319   b.lt  L_Skip                  // no cache or only instruction cache at this level
 320   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 321   isb                           // isb to sync the change to the CacheSizeID reg
 322   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 323   and   x2, x12, #0x7           // extract the line length field
 324   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 325   mov   x4, #0x400
 326   sub   x4, x4, #1
 327   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 328   clz   w5, w4                  // w5 is the bit position of the way size increment
 329   mov   x7, #0x00008000
 330   sub   x7, x7, #1
 331   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 332
 333 Loop2:
 334   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 335
 336 Loop3:
 337   lsl   x11, x9, x5
 338   orr   x0, x10, x11            // factor in the way number and cache number
 339   lsl   x11, x7, x2
 340   orr   x0, x0, x11             // factor in the index number
 341
 342   blr   x1                      // Goto requested cache operation
 343
 344   subs  x9, x9, #1              // decrement the way number
 345   b.ge  Loop3
 346   subs  x7, x7, #1              // decrement the index
 347   b.ge  Loop2
 348 L_Skip:
 349   add   x10, x10, #2            // increment the cache number
 350   cmp   x3, x10
 351   b.gt  Loop1
 352
 353 L_Finished:
 354   dsb   sy
 355   isb
 356   ldr   x30, [sp], #0x10
 357   ret
 358
 359
 360 ASM_PFX(ArmDataMemoryBarrier):
 361   dmb   sy
 362   ret
 363
 364
 365 ASM_PFX(ArmDataSynchronizationBarrier):
 366   dsb   sy
 367   ret
 368
 369
 370 ASM_PFX(ArmInstructionSynchronizationBarrier):
 371   isb
 372   ret
 373
 374
 375 ASM_PFX(ArmWriteVBar):
 376    EL1_OR_EL2_OR_EL3(x1)
 377 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 378    b     4f
 379 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 380    b     4f
 381 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 382 4: isb
 383    ret
 384
 385 ASM_PFX(ArmReadVBar):
 386    EL1_OR_EL2_OR_EL3(x1)
 387 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 388    ret
 389 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 390    ret
 391 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 392    ret
 393
 394
 395 ASM_PFX(ArmEnableVFP):
 396   // Check whether floating-point is implemented in the processor.
 397   mov   x1, x30                 // Save LR
 398   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 399   mov   x30, x1                 // Restore LR
 400   ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
 401   cmp   x0, #0                  // VFP is implemented if '0'.
 402   b.ne  4f                      // Exit if VFP not implemented.
 403   // FVP is implemented.
 404   // Make sure VFP exceptions are not trapped (to any exception level).
 405   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 406   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 407   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 408   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 409   EL1_OR_EL2_OR_EL3(x2)
 410 1:ret                           // Not configurable in EL1
 411 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 412   bic   x0, x0, x1
 413   msr   cptr_el2, x0
 414   ret
 415 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 416   bic   x0, x0, x1
 417   msr   cptr_el3, x0
 418 4:ret
 419
 420
 421 ASM_PFX(ArmCallWFI):
 422   wfi
 423   ret
 424
 425
 426 ASM_PFX(ArmReadMpidr):
 427   mrs   x0, mpidr_el1           // read EL1 MPIDR
 428   ret
 429
 430
 431 // Keep old function names for C compatibilty for now. Change later?
 432 ASM_PFX(ArmReadTpidrurw):
 433   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 434   ret
 435
 436
 437 // Keep old function names for C compatibilty for now. Change later?
 438 ASM_PFX(ArmWriteTpidrurw):
 439   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 440   ret
 441
 442
 443 // Arch timers are mandatory on AArch64
 444 ASM_PFX(ArmIsArchTimerImplemented):
 445   mov   x0, #1
 446   ret
 447
 448
 449 ASM_PFX(ArmReadIdPfr0):
 450   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 451   ret
 452
 453
 454 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 455 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 456 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 457 //    Not defined yet, but stick in here for now, should read all zeros.
 458 ASM_PFX(ArmReadIdPfr1):
 459   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 460   ret
 461
 462 // VOID ArmWriteHcr(UINTN Hcr)
 463 ASM_PFX(ArmWriteHcr):
 464   msr   hcr_el2, x0        // Write the passed HCR value
 465   ret
 466
 467 // UINTN ArmReadCurrentEL(VOID)
 468 ASM_PFX(ArmReadCurrentEL):
 469   mrs   x0, CurrentEL
 470   ret
 471
 472 ASM_FUNCTION_REMOVE_IF_UNREFERENCED