ArmPkg/Library/ArmLib/AArch64/AArch64Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <Chipset/AArch64.h>
  17 #include <AsmMacroIoLibV8.h>
  18
  19 .text
  20 .align 3
  21
  22 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  26 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  27 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  28 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  29 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  30 GCC_ASM_EXPORT (ArmEnableMmu)
  31 GCC_ASM_EXPORT (ArmDisableMmu)
  32 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  33 GCC_ASM_EXPORT (ArmMmuEnabled)
  34 GCC_ASM_EXPORT (ArmEnableDataCache)
  35 GCC_ASM_EXPORT (ArmDisableDataCache)
  36 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  37 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  38 GCC_ASM_EXPORT (ArmDisableAlignmentCheck)
  39 GCC_ASM_EXPORT (ArmEnableAlignmentCheck)
  40 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  41 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  42 GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
  43 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  44 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmReadVBar)
  48 GCC_ASM_EXPORT (ArmEnableVFP)
  49 GCC_ASM_EXPORT (ArmCallWFI)
  50 GCC_ASM_EXPORT (ArmReadMpidr)
  51 GCC_ASM_EXPORT (ArmReadTpidrurw)
  52 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  53 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  54 GCC_ASM_EXPORT (ArmReadIdPfr0)
  55 GCC_ASM_EXPORT (ArmReadIdPfr1)
  56 GCC_ASM_EXPORT (ArmWriteHcr)
  57 GCC_ASM_EXPORT (ArmReadCurrentEL)
  58
  59 .set CTRL_M_BIT,      (1 << 0)
  60 .set CTRL_A_BIT,      (1 << 1)
  61 .set CTRL_C_BIT,      (1 << 2)
  62 .set CTRL_I_BIT,      (1 << 12)
  63 .set CTRL_V_BIT,      (1 << 12)
  64 .set CPACR_VFP_BITS,  (3 << 20)
  65
  66 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  67   dc      ivac, x0    // Invalidate single data cache line
  68   ret
  69
  70
  71 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  72   dc      cvac, x0    // Clean single data cache line
  73   ret
  74
  75
  76 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  77   dc      civac, x0   // Clean and invalidate single data cache line
  78   ret
  79
  80
  81 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  82   dc      isw, x0     // Invalidate this line
  83   ret
  84
  85
  86 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  87   dc      cisw, x0    // Clean and Invalidate this line
  88   ret
  89
  90
  91 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  92   dc      csw, x0     // Clean this line
  93   ret
  94
  95
  96 ASM_PFX(ArmInvalidateInstructionCache):
  97   ic      iallu       // Invalidate entire instruction cache
  98   dsb     sy
  99   isb
 100   ret
 101
 102
 103 ASM_PFX(ArmEnableMmu):
 104    EL1_OR_EL2_OR_EL3(x1)
 105 1: mrs     x0, sctlr_el1       // Read System control register EL1
 106    b       4f
 107 2: mrs     x0, sctlr_el2       // Read System control register EL2
 108    b       4f
 109 3: mrs     x0, sctlr_el3       // Read System control register EL3
 110 4: orr     x0, x0, #CTRL_M_BIT // Set MMU enable bit
 111    EL1_OR_EL2_OR_EL3(x1)
 112 1: tlbi    vmalle1
 113    dsb     nsh
 114    isb
 115    msr     sctlr_el1, x0       // Write back
 116    b       4f
 117 2: tlbi    alle2
 118    dsb     nsh
 119    isb
 120    msr     sctlr_el2, x0       // Write back
 121    b       4f
 122 3: tlbi    alle3
 123    dsb     nsh
 124    isb
 125    msr     sctlr_el3, x0       // Write back
 126 4: isb
 127    ret
 128
 129
 130 ASM_PFX(ArmDisableMmu):
 131    EL1_OR_EL2_OR_EL3(x1)
 132 1: mrs     x0, sctlr_el1        // Read System Control Register EL1
 133    b       4f
 134 2: mrs     x0, sctlr_el2        // Read System Control Register EL2
 135    b       4f
 136 3: mrs     x0, sctlr_el3        // Read System Control Register EL3
 137 4: and     x0, x0, #~CTRL_M_BIT  // Clear MMU enable bit
 138    EL1_OR_EL2_OR_EL3(x1)
 139 1: msr     sctlr_el1, x0        // Write back
 140    tlbi    vmalle1
 141    b       4f
 142 2: msr     sctlr_el2, x0        // Write back
 143    tlbi    alle2
 144    b       4f
 145 3: msr     sctlr_el3, x0        // Write back
 146    tlbi    alle3
 147 4: dsb     sy
 148    isb
 149    ret
 150
 151
 152 ASM_PFX(ArmDisableCachesAndMmu):
 153    EL1_OR_EL2_OR_EL3(x1)
 154 1: mrs     x0, sctlr_el1        // Get control register EL1
 155    b       4f
 156 2: mrs     x0, sctlr_el2        // Get control register EL2
 157    b       4f
 158 3: mrs     x0, sctlr_el3        // Get control register EL3
 159 4: mov     x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT)  // Disable MMU, D & I caches
 160    and     x0, x0, x1
 161    EL1_OR_EL2_OR_EL3(x1)
 162 1: msr     sctlr_el1, x0        // Write back control register
 163    b       4f
 164 2: msr     sctlr_el2, x0        // Write back control register
 165    b       4f
 166 3: msr     sctlr_el3, x0        // Write back control register
 167 4: dsb     sy
 168    isb
 169    ret
 170
 171
 172 ASM_PFX(ArmMmuEnabled):
 173    EL1_OR_EL2_OR_EL3(x1)
 174 1: mrs     x0, sctlr_el1        // Get control register EL1
 175    b       4f
 176 2: mrs     x0, sctlr_el2        // Get control register EL2
 177    b       4f
 178 3: mrs     x0, sctlr_el3        // Get control register EL3
 179 4: and     x0, x0, #CTRL_M_BIT
 180    ret
 181
 182
 183 ASM_PFX(ArmEnableDataCache):
 184    EL1_OR_EL2_OR_EL3(x1)
 185 1: mrs     x0, sctlr_el1        // Get control register EL1
 186    b       4f
 187 2: mrs     x0, sctlr_el2        // Get control register EL2
 188    b       4f
 189 3: mrs     x0, sctlr_el3        // Get control register EL3
 190 4: orr     x0, x0, #CTRL_C_BIT  // Set C bit
 191    EL1_OR_EL2_OR_EL3(x1)
 192 1: msr     sctlr_el1, x0        // Write back control register
 193    b       4f
 194 2: msr     sctlr_el2, x0        // Write back control register
 195    b       4f
 196 3: msr     sctlr_el3, x0        // Write back control register
 197 4: dsb     sy
 198    isb
 199    ret
 200
 201
 202 ASM_PFX(ArmDisableDataCache):
 203    EL1_OR_EL2_OR_EL3(x1)
 204 1: mrs     x0, sctlr_el1        // Get control register EL1
 205    b       4f
 206 2: mrs     x0, sctlr_el2        // Get control register EL2
 207    b       4f
 208 3: mrs     x0, sctlr_el3        // Get control register EL3
 209 4: and     x0, x0, #~CTRL_C_BIT  // Clear C bit
 210    EL1_OR_EL2_OR_EL3(x1)
 211 1: msr     sctlr_el1, x0        // Write back control register
 212    b       4f
 213 2: msr     sctlr_el2, x0        // Write back control register
 214    b       4f
 215 3: msr     sctlr_el3, x0        // Write back control register
 216 4: dsb     sy
 217    isb
 218    ret
 219
 220
 221 ASM_PFX(ArmEnableInstructionCache):
 222    EL1_OR_EL2_OR_EL3(x1)
 223 1: mrs     x0, sctlr_el1        // Get control register EL1
 224    b       4f
 225 2: mrs     x0, sctlr_el2        // Get control register EL2
 226    b       4f
 227 3: mrs     x0, sctlr_el3        // Get control register EL3
 228 4: orr     x0, x0, #CTRL_I_BIT  // Set I bit
 229    EL1_OR_EL2_OR_EL3(x1)
 230 1: msr     sctlr_el1, x0        // Write back control register
 231    b       4f
 232 2: msr     sctlr_el2, x0        // Write back control register
 233    b       4f
 234 3: msr     sctlr_el3, x0        // Write back control register
 235 4: dsb     sy
 236    isb
 237    ret
 238
 239
 240 ASM_PFX(ArmDisableInstructionCache):
 241    EL1_OR_EL2_OR_EL3(x1)
 242 1: mrs     x0, sctlr_el1        // Get control register EL1
 243    b       4f
 244 2: mrs     x0, sctlr_el2        // Get control register EL2
 245    b       4f
 246 3: mrs     x0, sctlr_el3        // Get control register EL3
 247 4: and     x0, x0, #~CTRL_I_BIT  // Clear I bit
 248    EL1_OR_EL2_OR_EL3(x1)
 249 1: msr     sctlr_el1, x0        // Write back control register
 250    b       4f
 251 2: msr     sctlr_el2, x0        // Write back control register
 252    b       4f
 253 3: msr     sctlr_el3, x0        // Write back control register
 254 4: dsb     sy
 255    isb
 256    ret
 257
 258
 259 ASM_PFX(ArmEnableAlignmentCheck):
 260    EL1_OR_EL2(x1)
 261 1: mrs     x0, sctlr_el1        // Get control register EL1
 262    b       3f
 263 2: mrs     x0, sctlr_el2        // Get control register EL2
 264 3: orr     x0, x0, #CTRL_A_BIT  // Set A (alignment check) bit
 265    EL1_OR_EL2(x1)
 266 1: msr     sctlr_el1, x0        // Write back control register
 267    b       3f
 268 2: msr     sctlr_el2, x0        // Write back control register
 269 3: dsb     sy
 270    isb
 271    ret
 272
 273
 274 ASM_PFX(ArmDisableAlignmentCheck):
 275    EL1_OR_EL2_OR_EL3(x1)
 276 1: mrs     x0, sctlr_el1        // Get control register EL1
 277    b       4f
 278 2: mrs     x0, sctlr_el2        // Get control register EL2
 279    b       4f
 280 3: mrs     x0, sctlr_el3        // Get control register EL3
 281 4: and     x0, x0, #~CTRL_A_BIT  // Clear A (alignment check) bit
 282    EL1_OR_EL2_OR_EL3(x1)
 283 1: msr     sctlr_el1, x0        // Write back control register
 284    b       4f
 285 2: msr     sctlr_el2, x0        // Write back control register
 286    b       4f
 287 3: msr     sctlr_el3, x0        // Write back control register
 288 4: dsb     sy
 289    isb
 290    ret
 291
 292
 293 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now
 294 ASM_PFX(ArmEnableBranchPrediction):
 295   ret
 296
 297
 298 // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now.
 299 ASM_PFX(ArmDisableBranchPrediction):
 300   ret
 301
 302
 303 ASM_PFX(AArch64AllDataCachesOperation):
 304 // We can use regs 0-7 and 9-15 without having to save/restore.
 305 // Save our link register on the stack. - The stack must always be quad-word aligned
 306   str   x30, [sp, #-16]!
 307   mov   x1, x0                  // Save Function call in x1
 308   mrs   x6, clidr_el1           // Read EL1 CLIDR
 309   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)
 310   lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the
 311                                 // right to ease the access to CSSELR and the Set/Way operation.
 312   cbz   x3, L_Finished          // No need to clean if LoC is 0
 313   mov   x10, #0                 // Start clean at cache level 0
 314
 315 Loop1:
 316   add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info
 317   lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level
 318   and   x12, x12, #7            // get those 3 bits alone
 319   cmp   x12, #2                 // what cache at this level?
 320   b.lt  L_Skip                  // no cache or only instruction cache at this level
 321   msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)
 322   isb                           // isb to sync the change to the CacheSizeID reg
 323   mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)
 324   and   x2, x12, #0x7           // extract the line length field
 325   add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)
 326   mov   x4, #0x400
 327   sub   x4, x4, #1
 328   and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)
 329   clz   w5, w4                  // w5 is the bit position of the way size increment
 330   mov   x7, #0x00008000
 331   sub   x7, x7, #1
 332   and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)
 333
 334 Loop2:
 335   mov   x9, x4                  // x9 working copy of the max way size (right aligned)
 336
 337 Loop3:
 338   lsl   x11, x9, x5
 339   orr   x0, x10, x11            // factor in the way number and cache number
 340   lsl   x11, x7, x2
 341   orr   x0, x0, x11             // factor in the index number
 342
 343   blr   x1                      // Goto requested cache operation
 344
 345   subs  x9, x9, #1              // decrement the way number
 346   b.ge  Loop3
 347   subs  x7, x7, #1              // decrement the index
 348   b.ge  Loop2
 349 L_Skip:
 350   add   x10, x10, #2            // increment the cache number
 351   cmp   x3, x10
 352   b.gt  Loop1
 353
 354 L_Finished:
 355   dsb   sy
 356   isb
 357   ldr   x30, [sp], #0x10
 358   ret
 359
 360
 361 ASM_PFX(ArmDataMemoryBarrier):
 362   dmb   sy
 363   ret
 364
 365
 366 ASM_PFX(ArmDataSynchronizationBarrier):
 367 ASM_PFX(ArmDrainWriteBuffer):
 368   dsb   sy
 369   ret
 370
 371
 372 ASM_PFX(ArmInstructionSynchronizationBarrier):
 373   isb
 374   ret
 375
 376
 377 ASM_PFX(ArmWriteVBar):
 378    EL1_OR_EL2_OR_EL3(x1)
 379 1: msr   vbar_el1, x0            // Set the Address of the EL1 Vector Table in the VBAR register
 380    b     4f
 381 2: msr   vbar_el2, x0            // Set the Address of the EL2 Vector Table in the VBAR register
 382    b     4f
 383 3: msr   vbar_el3, x0            // Set the Address of the EL3 Vector Table in the VBAR register
 384 4: isb
 385    ret
 386
 387 ASM_PFX(ArmReadVBar):
 388    EL1_OR_EL2_OR_EL3(x1)
 389 1: mrs   x0, vbar_el1            // Set the Address of the EL1 Vector Table in the VBAR register
 390    ret
 391 2: mrs   x0, vbar_el2            // Set the Address of the EL2 Vector Table in the VBAR register
 392    ret
 393 3: mrs   x0, vbar_el3            // Set the Address of the EL3 Vector Table in the VBAR register
 394    ret
 395
 396
 397 ASM_PFX(ArmEnableVFP):
 398   // Check whether floating-point is implemented in the processor.
 399   mov   x1, x30                 // Save LR
 400   bl    ArmReadIdPfr0           // Read EL1 Processor Feature Register (PFR0)
 401   mov   x30, x1                 // Restore LR
 402   ands  x0, x0, #AARCH64_PFR0_FP// Extract bits indicating VFP implementation
 403   cmp   x0, #0                  // VFP is implemented if '0'.
 404   b.ne  4f                      // Exit if VFP not implemented.
 405   // FVP is implemented.
 406   // Make sure VFP exceptions are not trapped (to any exception level).
 407   mrs   x0, cpacr_el1           // Read EL1 Coprocessor Access Control Register (CPACR)
 408   orr   x0, x0, #CPACR_VFP_BITS // Disable FVP traps to EL1
 409   msr   cpacr_el1, x0           // Write back EL1 Coprocessor Access Control Register (CPACR)
 410   mov   x1, #AARCH64_CPTR_TFP   // TFP Bit for trapping VFP Exceptions
 411   EL1_OR_EL2_OR_EL3(x2)
 412 1:ret                           // Not configurable in EL1
 413 2:mrs   x0, cptr_el2            // Disable VFP traps to EL2
 414   bic   x0, x0, x1
 415   msr   cptr_el2, x0
 416   ret
 417 3:mrs   x0, cptr_el3            // Disable VFP traps to EL3
 418   bic   x0, x0, x1
 419   msr   cptr_el3, x0
 420 4:ret
 421
 422
 423 ASM_PFX(ArmCallWFI):
 424   wfi
 425   ret
 426
 427
 428 ASM_PFX(ArmReadMpidr):
 429   mrs   x0, mpidr_el1           // read EL1 MPIDR
 430   ret
 431
 432
 433 // Keep old function names for C compatibilty for now. Change later?
 434 ASM_PFX(ArmReadTpidrurw):
 435   mrs   x0, tpidr_el0           // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 436   ret
 437
 438
 439 // Keep old function names for C compatibilty for now. Change later?
 440 ASM_PFX(ArmWriteTpidrurw):
 441   msr   tpidr_el0, x0           // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)
 442   ret
 443
 444
 445 // Arch timers are mandatory on AArch64
 446 ASM_PFX(ArmIsArchTimerImplemented):
 447   mov   x0, #1
 448   ret
 449
 450
 451 ASM_PFX(ArmReadIdPfr0):
 452   mrs   x0, id_aa64pfr0_el1   // Read ID_AA64PFR0 Register
 453   ret
 454
 455
 456 // Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?
 457 // A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.
 458 //    See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c
 459 //    Not defined yet, but stick in here for now, should read all zeros.
 460 ASM_PFX(ArmReadIdPfr1):
 461   mrs   x0, id_aa64pfr1_el1   // Read ID_PFR1 Register
 462   ret
 463
 464 // VOID ArmWriteHcr(UINTN Hcr)
 465 ASM_PFX(ArmWriteHcr):
 466   msr   hcr_el2, x0        // Write the passed HCR value
 467   ret
 468
 469 // UINTN ArmReadCurrentEL(VOID)
 470 ASM_PFX(ArmReadCurrentEL):
 471   mrs   x0, CurrentEL
 472   ret
 473
 474 ASM_FUNCTION_REMOVE_IF_UNREFERENCED