1ef2f61f5979013a63247eafb19b0e87f0d6d894
[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / ArmLibSupport.S
1 #------------------------------------------------------------------------------
2 #
3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
6 #
7 # This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
11 #
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #
15 #------------------------------------------------------------------------------
16
17 #include <AsmMacroIoLibV8.h>
18
19 .set DAIF_RD_FIQ_BIT, (1 << 6)
20 .set DAIF_RD_IRQ_BIT, (1 << 7)
21
22 ASM_FUNC(ArmReadMidr)
23 mrs x0, midr_el1 // Read from Main ID Register (MIDR)
24 ret
25
26 ASM_FUNC(ArmCacheInfo)
27 mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
28 ret
29
30 ASM_FUNC(ArmGetInterruptState)
31 mrs x0, daif
32 tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)
33 cset w0, eq // if Z=1 return 1, else 0
34 ret
35
36 ASM_FUNC(ArmGetFiqState)
37 mrs x0, daif
38 tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)
39 cset w0, eq // if Z=1 return 1, else 0
40 ret
41
42 ASM_FUNC(ArmWriteCpacr)
43 msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
44 ret
45
46 ASM_FUNC(ArmWriteAuxCr)
47 EL1_OR_EL2(x1)
48 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
49 ret
50 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
51 ret
52
53 ASM_FUNC(ArmReadAuxCr)
54 EL1_OR_EL2(x1)
55 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
56 ret
57 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
58 ret
59
60 ASM_FUNC(ArmSetTTBR0)
61 EL1_OR_EL2_OR_EL3(x1)
62 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
63 b 4f
64 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)
65 b 4f
66 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)
67 4:isb
68 ret
69
70 ASM_FUNC(ArmGetTTBR0BaseAddress)
71 EL1_OR_EL2(x1)
72 1:mrs x0, ttbr0_el1
73 b 3f
74 2:mrs x0, ttbr0_el2
75 3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */
76 isb
77 ret
78
79 ASM_FUNC(ArmGetTCR)
80 EL1_OR_EL2_OR_EL3(x1)
81 1:mrs x0, tcr_el1
82 b 4f
83 2:mrs x0, tcr_el2
84 b 4f
85 3:mrs x0, tcr_el3
86 4:isb
87 ret
88
89 ASM_FUNC(ArmSetTCR)
90 EL1_OR_EL2_OR_EL3(x1)
91 1:msr tcr_el1, x0
92 b 4f
93 2:msr tcr_el2, x0
94 b 4f
95 3:msr tcr_el3, x0
96 4:isb
97 ret
98
99 ASM_FUNC(ArmGetMAIR)
100 EL1_OR_EL2_OR_EL3(x1)
101 1:mrs x0, mair_el1
102 b 4f
103 2:mrs x0, mair_el2
104 b 4f
105 3:mrs x0, mair_el3
106 4:isb
107 ret
108
109 ASM_FUNC(ArmSetMAIR)
110 EL1_OR_EL2_OR_EL3(x1)
111 1:msr mair_el1, x0
112 b 4f
113 2:msr mair_el2, x0
114 b 4f
115 3:msr mair_el3, x0
116 4:isb
117 ret
118
119
120 //
121 //VOID
122 //ArmUpdateTranslationTableEntry (
123 // IN VOID *TranslationTableEntry // X0
124 // IN VOID *MVA // X1
125 // );
126 ASM_FUNC(ArmUpdateTranslationTableEntry)
127 dc civac, x0 // Clean and invalidate data line
128 dsb sy
129 EL1_OR_EL2_OR_EL3(x0)
130 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
131 b 4f
132 2: tlbi vae2, x1 // TLB Invalidate VA , EL2
133 b 4f
134 3: tlbi vae3, x1 // TLB Invalidate VA , EL3
135 4: dsb sy
136 isb
137 ret
138
139 ASM_FUNC(ArmInvalidateTlb)
140 EL1_OR_EL2_OR_EL3(x0)
141 1: tlbi vmalle1
142 b 4f
143 2: tlbi alle2
144 b 4f
145 3: tlbi alle3
146 4: dsb sy
147 isb
148 ret
149
150 ASM_FUNC(ArmWriteCptr)
151 msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
152 ret
153
154 ASM_FUNC(ArmWriteScr)
155 msr scr_el3, x0 // Secure configuration register EL3
156 isb
157 ret
158
159 ASM_FUNC(ArmWriteMVBar)
160 msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3
161 ret
162
163 ASM_FUNC(ArmCallWFE)
164 wfe
165 ret
166
167 ASM_FUNC(ArmCallSEV)
168 sev
169 ret
170
171 ASM_FUNC(ArmReadCpuActlr)
172 mrs x0, S3_1_c15_c2_0
173 ret
174
175 ASM_FUNC(ArmWriteCpuActlr)
176 msr S3_1_c15_c2_0, x0
177 dsb sy
178 isb
179 ret
180
181 ASM_FUNC(ArmReadSctlr)
182 EL1_OR_EL2_OR_EL3(x1)
183 1:mrs x0, sctlr_el1
184 ret
185 2:mrs x0, sctlr_el2
186 ret
187 3:mrs x0, sctlr_el3
188 4:ret
189
190 ASM_FUNC(ArmWriteSctlr)
191 EL1_OR_EL2_OR_EL3(x1)
192 1:msr sctlr_el1, x0
193 ret
194 2:msr sctlr_el2, x0
195 ret
196 3:msr sctlr_el3, x0
197 4:ret
198
199 ASM_FUNCTION_REMOVE_IF_UNREFERENCED