1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
7 # This program and the accompanying materials
8 # are licensed and made available under the terms and conditions of the BSD License
9 # which accompanies this distribution. The full text of the license may be found at
10 # http://opensource.org/licenses/bsd-license.php
12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #------------------------------------------------------------------------------
17 #include <AsmMacroIoLibV8.h>
19 .set DAIF_RD_FIQ_BIT, (1 << 6)
20 .set DAIF_RD_IRQ_BIT, (1 << 7)
23 mrs x0, midr_el1 // Read from Main ID Register (MIDR)
26 ASM_FUNC(ArmCacheInfo)
27 mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
30 ASM_FUNC(ArmGetInterruptState)
32 tst w0, #DAIF_RD_IRQ_BIT // Check if IRQ is enabled. Enabled if 0 (Z=1)
33 cset w0, eq // if Z=1 return 1, else 0
36 ASM_FUNC(ArmGetFiqState)
38 tst w0, #DAIF_RD_FIQ_BIT // Check if FIQ is enabled. Enabled if 0 (Z=1)
39 cset w0, eq // if Z=1 return 1, else 0
42 ASM_FUNC(ArmWriteCpacr)
43 msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
46 ASM_FUNC(ArmWriteAuxCr)
48 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
50 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
53 ASM_FUNC(ArmReadAuxCr)
55 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
57 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
62 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
64 2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)
66 3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)
70 ASM_FUNC(ArmGetTTBR0BaseAddress)
75 3:and x0, x0, 0xFFFFFFFFFFFF /* Look at bottom 48 bits */
100 EL1_OR_EL2_OR_EL3(x1)
110 EL1_OR_EL2_OR_EL3(x1)
122 //ArmUpdateTranslationTableEntry (
123 // IN VOID *TranslationTableEntry // X0
124 // IN VOID *MVA // X1
126 ASM_FUNC(ArmUpdateTranslationTableEntry)
127 dc civac, x0 // Clean and invalidate data line
129 EL1_OR_EL2_OR_EL3(x0)
130 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
132 2: tlbi vae2, x1 // TLB Invalidate VA , EL2
134 3: tlbi vae3, x1 // TLB Invalidate VA , EL3
139 ASM_FUNC(ArmInvalidateTlb)
140 EL1_OR_EL2_OR_EL3(x0)
150 ASM_FUNC(ArmWriteCptr)
151 msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
154 ASM_FUNC(ArmWriteScr)
155 msr scr_el3, x0 // Secure configuration register EL3
159 ASM_FUNC(ArmWriteMVBar)
160 msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3
171 ASM_FUNC(ArmReadCpuActlr)
172 mrs x0, S3_1_c15_c2_0
175 ASM_FUNC(ArmWriteCpuActlr)
176 msr S3_1_c15_c2_0, x0
181 ASM_FUNC(ArmReadSctlr)
182 EL1_OR_EL2_OR_EL3(x1)
190 ASM_FUNC(ArmWriteSctlr)
191 EL1_OR_EL2_OR_EL3(x1)
199 ASM_FUNC(ArmGetPhysicalAddressBits)
200 mrs x0, id_aa64mmfr0_el1
207 // Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the
208 // physical address space support on this CPU:
209 // 0 == 32 bits, 1 == 36 bits, etc etc
210 // 7 and up are reserved
213 .byte 32, 36, 40, 42, 44, 48, 52, 0
214 .byte 0, 0, 0, 0, 0, 0, 0, 0
216 ASM_FUNCTION_REMOVE_IF_UNREFERENCED