ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 3
  20
  21 GCC_ASM_EXPORT (ArmIsMpCore)
  22 GCC_ASM_EXPORT (ArmEnableAsynchronousAbort)
  23 GCC_ASM_EXPORT (ArmDisableAsynchronousAbort)
  24 GCC_ASM_EXPORT (ArmEnableIrq)
  25 GCC_ASM_EXPORT (ArmDisableIrq)
  26 GCC_ASM_EXPORT (ArmEnableFiq)
  27 GCC_ASM_EXPORT (ArmDisableFiq)
  28 GCC_ASM_EXPORT (ArmEnableInterrupts)
  29 GCC_ASM_EXPORT (ArmDisableInterrupts)
  30 GCC_ASM_EXPORT (ArmDisableAllExceptions)
  31 GCC_ASM_EXPORT (ReadCCSIDR)
  32 GCC_ASM_EXPORT (ReadCLIDR)
  33
  34 #------------------------------------------------------------------------------
  35
  36 .set MPIDR_U_BIT,    (30)
  37 .set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)
  38 .set DAIF_FIQ_BIT,   (1 << 0)
  39 .set DAIF_IRQ_BIT,   (1 << 1)
  40 .set DAIF_ABORT_BIT, (1 << 2)
  41 .set DAIF_DEBUG_BIT, (1 << 3)
  42 .set DAIF_INT_BITS,  (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
  43 .set DAIF_ALL,       (DAIF_DEBUG_BIT | DAIF_ABORT_BIT | DAIF_INT_BITS)
  44
  45
  46 ASM_PFX(ArmIsMpCore):
  47   mrs   x0, mpidr_el1         // Read EL1 Mutliprocessor Affinty Reg (MPIDR)
  48   and   x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system
  49   lsr   x0, x0, #MPIDR_U_BIT
  50   eor   x0, x0, #1
  51   ret
  52
  53
  54 ASM_PFX(ArmEnableAsynchronousAbort):
  55   msr   daifclr, #DAIF_ABORT_BIT
  56   isb
  57   ret
  58
  59
  60 ASM_PFX(ArmDisableAsynchronousAbort):
  61   msr   daifset, #DAIF_ABORT_BIT
  62   isb
  63   ret
  64
  65
  66 ASM_PFX(ArmEnableIrq):
  67   msr   daifclr, #DAIF_IRQ_BIT
  68   isb
  69   ret
  70
  71
  72 ASM_PFX(ArmDisableIrq):
  73   msr   daifset, #DAIF_IRQ_BIT
  74   isb
  75   ret
  76
  77
  78 ASM_PFX(ArmEnableFiq):
  79   msr   daifclr, #DAIF_FIQ_BIT
  80   isb
  81   ret
  82
  83
  84 ASM_PFX(ArmDisableFiq):
  85   msr   daifset, #DAIF_FIQ_BIT
  86   isb
  87   ret
  88
  89
  90 ASM_PFX(ArmEnableInterrupts):
  91   msr   daifclr, #DAIF_INT_BITS
  92   isb
  93   ret
  94
  95
  96 ASM_PFX(ArmDisableInterrupts):
  97   msr   daifset, #DAIF_INT_BITS
  98   isb
  99   ret
 100
 101
 102 ASM_PFX(ArmDisableAllExceptions):
 103   msr   daifset, #DAIF_ALL
 104   isb
 105   ret
 106
 107
 108 // UINT32
 109 // ReadCCSIDR (
 110 //   IN UINT32 CSSELR
 111 //   )
 112 ASM_PFX(ReadCCSIDR):
 113   msr   csselr_el1, x0        // Write Cache Size Selection Register (CSSELR)
 114   isb
 115   mrs   x0, ccsidr_el1        // Read current Cache Size ID Register (CCSIDR)
 116   ret
 117
 118
 119 // UINT32
 120 // ReadCLIDR (
 121 //   IN UINT32 CSSELR
 122 //   )
 123 ASM_PFX(ReadCLIDR):
 124   mrs   x0, clidr_el1         // Read Cache Level ID Register
 125   ret
 126
 127 ASM_FUNCTION_REMOVE_IF_UNREFERENCED