ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # This program and the accompanying materials
   8 # are licensed and made available under the terms and conditions of the BSD License
   9 # which accompanies this distribution.  The full text of the license may be found at
  10 # http://opensource.org/licenses/bsd-license.php
  11 #
  12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #------------------------------------------------------------------------------
  16
  17 #include <AsmMacroIoLib.h>
  18
  19 ASM_FUNC(ArmReadMidr)
  20   mrc     p15,0,R0,c0,c0,0
  21   bx      LR
  22
  23 ASM_FUNC(ArmCacheInfo)
  24   mrc     p15,0,R0,c0,c0,1
  25   bx      LR
  26
  27 ASM_FUNC(ArmGetInterruptState)
  28   mrs     R0,CPSR
  29   tst     R0,#0x80      @Check if IRQ is enabled.
  30   moveq   R0,#1
  31   movne   R0,#0
  32   bx      LR
  33
  34 ASM_FUNC(ArmGetFiqState)
  35   mrs     R0,CPSR
  36   tst     R0,#0x40      @Check if FIQ is enabled.
  37   moveq   R0,#1
  38   movne   R0,#0
  39   bx      LR
  40
  41 ASM_FUNC(ArmSetDomainAccessControl)
  42   mcr     p15,0,r0,c3,c0,0
  43   bx      lr
  44
  45 ASM_FUNC(CPSRMaskInsert)    @ on entry, r0 is the mask and r1 is the field to insert
  46   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  47   mov     r3, sp            @ copy the stack pointer into a non-banked register
  48   mrs     r2, cpsr          @ read the cpsr
  49   bic     r2, r2, r0        @ clear mask in the cpsr
  50   and     r1, r1, r0        @ clear bits outside the mask in the input
  51   orr     r2, r2, r1        @ set field
  52   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  53   isb
  54   mov     sp, r3            @ restore stack pointer
  55   ldmfd   sp!, {r4-r12, lr} @ restore registers
  56   bx      lr                @ return (hopefully thumb-safe!)
  57
  58 ASM_FUNC(CPSRRead)
  59   mrs     r0, cpsr
  60   bx      lr
  61
  62 ASM_FUNC(ArmReadCpacr)
  63   mrc     p15, 0, r0, c1, c0, 2
  64   bx      lr
  65
  66 ASM_FUNC(ArmWriteCpacr)
  67   mcr     p15, 0, r0, c1, c0, 2
  68   isb
  69   bx      lr
  70
  71 ASM_FUNC(ArmWriteAuxCr)
  72   mcr     p15, 0, r0, c1, c0, 1
  73   bx      lr
  74
  75 ASM_FUNC(ArmReadAuxCr)
  76   mrc     p15, 0, r0, c1, c0, 1
  77   bx      lr
  78
  79 ASM_FUNC(ArmSetTTBR0)
  80   mcr     p15,0,r0,c2,c0,0
  81   isb
  82   bx      lr
  83
  84 ASM_FUNC(ArmSetTTBCR)
  85   mcr     p15, 0, r0, c2, c0, 2
  86   isb
  87   bx      lr
  88
  89 ASM_FUNC(ArmGetTTBR0BaseAddress)
  90   mrc     p15,0,r0,c2,c0,0
  91   MOV32   (r1, 0xFFFFC000)
  92   and     r0, r0, r1
  93   isb
  94   bx      lr
  95
  96 //
  97 //VOID
  98 //ArmUpdateTranslationTableEntry (
  99 //  IN VOID  *TranslationTableEntry  // R0
 100 //  IN VOID  *MVA                    // R1
 101 //  );
 102 ASM_FUNC(ArmUpdateTranslationTableEntry)
 103   mcr     p15,0,R0,c7,c14,1     @ DCCIMVAC Clean data cache by MVA
 104   dsb
 105   mcr     p15,0,R1,c8,c7,1      @ TLBIMVA TLB Invalidate MVA
 106   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 107   dsb
 108   isb
 109   bx      lr
 110
 111 ASM_FUNC(ArmInvalidateTlb)
 112   mov     r0,#0
 113   mcr     p15,0,r0,c8,c7,0
 114   mcr     p15,0,R9,c7,c5,6      @ BPIALL Invalidate Branch predictor array. R9 == NoOp
 115   dsb
 116   isb
 117   bx      lr
 118
 119 ASM_FUNC(ArmReadScr)
 120   mrc     p15, 0, r0, c1, c1, 0
 121   bx      lr
 122
 123 ASM_FUNC(ArmWriteScr)
 124   mcr     p15, 0, r0, c1, c1, 0
 125   isb
 126   bx      lr
 127
 128 ASM_FUNC(ArmReadHVBar)
 129   mrc     p15, 4, r0, c12, c0, 0
 130   bx      lr
 131
 132 ASM_FUNC(ArmWriteHVBar)
 133   mcr     p15, 4, r0, c12, c0, 0
 134   bx      lr
 135
 136 ASM_FUNC(ArmReadMVBar)
 137   mrc     p15, 0, r0, c12, c0, 1
 138   bx      lr
 139
 140 ASM_FUNC(ArmWriteMVBar)
 141   mcr     p15, 0, r0, c12, c0, 1
 142   bx      lr
 143
 144 ASM_FUNC(ArmCallWFE)
 145   wfe
 146   bx      lr
 147
 148 ASM_FUNC(ArmCallSEV)
 149   sev
 150   bx      lr
 151
 152 ASM_FUNC(ArmReadSctlr)
 153   mrc     p15, 0, r0, c1, c0, 0      @ Read SCTLR into R0 (Read control register configuration data)
 154   bx      lr
 155
 156 ASM_FUNC(ArmWriteSctlr)
 157   mcr     p15, 0, r0, c1, c0, 0
 158   bx      lr
 159
 160 ASM_FUNC(ArmReadCpuActlr)
 161   mrc     p15, 0, r0, c1, c0, 1
 162   bx      lr
 163
 164 ASM_FUNC(ArmWriteCpuActlr)
 165   mcr     p15, 0, r0, c1, c0, 1
 166   dsb
 167   isb
 168   bx      lr
 169
 170 ASM_FUNCTION_REMOVE_IF_UNREFERENCED