1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 //------------------------------------------------------------------------------
16 INCLUDE AsmMacroIoLib.inc
19 INCLUDE AsmMacroExport.inc
21 RVCT_ASM_EXPORT ArmReadMidr
25 RVCT_ASM_EXPORT ArmCacheInfo
29 RVCT_ASM_EXPORT ArmGetInterruptState
31 tst R0,#0x80 // Check if IRQ is enabled.
36 RVCT_ASM_EXPORT ArmGetFiqState
38 tst R0,#0x40 // Check if FIQ is enabled.
43 RVCT_ASM_EXPORT ArmSetDomainAccessControl
47 RVCT_ASM_EXPORT CPSRMaskInsert
48 stmfd sp!, {r4-r12, lr} // save all the banked registers
49 mov r3, sp // copy the stack pointer into a non-banked register
50 mrs r2, cpsr // read the cpsr
51 bic r2, r2, r0 // clear mask in the cpsr
52 and r1, r1, r0 // clear bits outside the mask in the input
53 orr r2, r2, r1 // set field
54 msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
56 mov sp, r3 // restore stack pointer
57 ldmfd sp!, {r4-r12, lr} // restore registers
58 bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
60 RVCT_ASM_EXPORT CPSRRead
64 RVCT_ASM_EXPORT ArmReadCpacr
65 mrc p15, 0, r0, c1, c0, 2
68 RVCT_ASM_EXPORT ArmWriteCpacr
69 mcr p15, 0, r0, c1, c0, 2
73 RVCT_ASM_EXPORT ArmWriteAuxCr
74 mcr p15, 0, r0, c1, c0, 1
77 RVCT_ASM_EXPORT ArmReadAuxCr
78 mrc p15, 0, r0, c1, c0, 1
81 RVCT_ASM_EXPORT ArmSetTTBR0
86 RVCT_ASM_EXPORT ArmSetTTBCR
87 mcr p15, 0, r0, c2, c0, 2
91 RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
100 //ArmUpdateTranslationTableEntry (
101 // IN VOID *TranslationTableEntry // R0
102 // IN VOID *MVA // R1
104 RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry
105 mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
107 mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
108 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
113 RVCT_ASM_EXPORT ArmInvalidateTlb
116 mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
121 RVCT_ASM_EXPORT ArmReadScr
122 mrc p15, 0, r0, c1, c1, 0
125 RVCT_ASM_EXPORT ArmWriteScr
126 mcr p15, 0, r0, c1, c1, 0
130 RVCT_ASM_EXPORT ArmReadHVBar
131 mrc p15, 4, r0, c12, c0, 0
134 RVCT_ASM_EXPORT ArmWriteHVBar
135 mcr p15, 4, r0, c12, c0, 0
138 RVCT_ASM_EXPORT ArmReadMVBar
139 mrc p15, 0, r0, c12, c0, 1
142 RVCT_ASM_EXPORT ArmWriteMVBar
143 mcr p15, 0, r0, c12, c0, 1
146 RVCT_ASM_EXPORT ArmCallWFE
150 RVCT_ASM_EXPORT ArmCallSEV
154 RVCT_ASM_EXPORT ArmReadSctlr
155 mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
158 RVCT_ASM_EXPORT ArmWriteSctlr
159 mcr p15, 0, r0, c1, c0, 0
162 RVCT_ASM_EXPORT ArmReadCpuActlr
163 mrc p15, 0, r0, c1, c0, 1
166 RVCT_ASM_EXPORT ArmWriteCpuActlr
167 mcr p15, 0, r0, c1, c0, 1