ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Chipset/ARM1176JZ-S.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/BaseMemoryLib.h>
  18 #include <Library/MemoryAllocationLib.h>
  19
  20 VOID
  21 FillTranslationTable (
  22   IN  UINT32                        *TranslationTable,
  23   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
  24   )
  25 {
  26   UINT32  *Entry;
  27   UINTN   Sections;
  28   UINTN   Index;
  29   UINT32  Attributes;
  30   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
  31
  32   switch (MemoryRegion->Attributes) {
  33     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  34       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
  35       break;
  36     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
  37       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
  38       break;
  39     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
  40     default:
  41       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
  42       break;
  43   }
  44
  45   Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
  46   Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
  47
  48   for (Index = 0; Index < Sections; Index++)
  49   {
  50     *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
  51     PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
  52   }
  53 }
  54
  55 VOID
  56 EFIAPI
  57 ArmConfigureMmu (
  58   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
  59   OUT VOID                          **TranslationTableBase OPTIONAL,
  60   OUT UINTN                         *TranslationTableSize  OPTIONAL
  61   )
  62 {
  63   VOID  *TranslationTable;
  64
  65   // Allocate pages for translation table.
  66   TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
  67   TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
  68
  69   if (TranslationTableBase != NULL) {
  70     *TranslationTableBase = TranslationTable;
  71   }
  72
  73   if (TranslationTableBase != NULL) {
  74     *TranslationTableSize = TRANSLATION_TABLE_SIZE;
  75   }
  76
  77   ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
  78
  79   ArmCleanInvalidateDataCache();
  80   ArmInvalidateInstructionCache();
  81   ArmInvalidateTlb();
  82
  83   ArmDisableDataCache();
  84   ArmDisableInstructionCache();
  85   ArmDisableMmu();
  86
  87   // Make sure nothing sneaked into the cache
  88   ArmCleanInvalidateDataCache();
  89   ArmInvalidateInstructionCache();
  90
  91   while (MemoryTable->Length != 0) {
  92     FillTranslationTable(TranslationTable, MemoryTable);
  93     MemoryTable++;
  94   }
  95
  96   ArmSetTranslationTableBaseAddress(TranslationTable);
  97
  98   ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
  99                             DOMAIN_ACCESS_CONTROL_NONE(14) |
 100                             DOMAIN_ACCESS_CONTROL_NONE(13) |
 101                             DOMAIN_ACCESS_CONTROL_NONE(12) |
 102                             DOMAIN_ACCESS_CONTROL_NONE(11) |
 103                             DOMAIN_ACCESS_CONTROL_NONE(10) |
 104                             DOMAIN_ACCESS_CONTROL_NONE( 9) |
 105                             DOMAIN_ACCESS_CONTROL_NONE( 8) |
 106                             DOMAIN_ACCESS_CONTROL_NONE( 7) |
 107                             DOMAIN_ACCESS_CONTROL_NONE( 6) |
 108                             DOMAIN_ACCESS_CONTROL_NONE( 5) |
 109                             DOMAIN_ACCESS_CONTROL_NONE( 4) |
 110                             DOMAIN_ACCESS_CONTROL_NONE( 3) |
 111                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
 112                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
 113                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
 114
 115   ArmEnableInstructionCache();
 116   ArmEnableDataCache();
 117   ArmEnableMmu();
 118 }
 119
 120
 121
 122