ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17 .globl ASM_PFX(ArmCleanInvalidateDataCache)
  18 .globl ASM_PFX(ArmCleanDataCache)
  19 .globl ASM_PFX(ArmInvalidateDataCache)
  20 .globl ASM_PFX(ArmInvalidateInstructionCache)
  21 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
  22 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
  23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
  24 .globl ASM_PFX(ArmEnableMmu)
  25 .globl ASM_PFX(ArmDisableMmu)
  26 .globl ASM_PFX(ArmMmuEnabled)
  27 .globl ASM_PFX(ArmEnableDataCache)
  28 .globl ASM_PFX(ArmDisableDataCache)
  29 .globl ASM_PFX(ArmEnableInstructionCache)
  30 .globl ASM_PFX(ArmDisableInstructionCache)
  31 .globl ASM_PFX(ArmEnableBranchPrediction)
  32 .globl ASM_PFX(ArmDisableBranchPrediction)
  33 .globl ASM_PFX(ArmDataMemoryBarrier)
  34 .globl ASM_PFX(ArmDataSyncronizationBarrier)
  35 .globl ASM_PFX(ArmInstructionSynchronizationBarrier)
  36
  37
  38 .set DC_ON, (0x1<<2)
  39 .set IC_ON, (0x1<<12)
  40 .set XP_ON, (0x1<<23)
  41
  42 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  43   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  44   bx      lr
  45
  46
  47 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  48   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  49   bx      lr
  50
  51
  52 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  53   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  54   bx      lr
  55
  56
  57 ASM_PFX(ArmCleanDataCache):
  58   mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
  59   bx      lr
  60
  61
  62 ASM_PFX(ArmCleanInvalidateDataCache):
  63   mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
  64   bx      lr
  65
  66
  67 ASM_PFX(ArmInvalidateDataCache):
  68   mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
  69   bx      lr
  70
  71
  72 ASM_PFX(ArmInvalidateInstructionCache):
  73   mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
  74   mov     R0,#0
  75   mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
  76   bx      lr
  77
  78 ASM_PFX(ArmEnableMmu):
  79   mrc     p15,0,R0,c1,c0,0
  80   orr     R0,R0,#1
  81   mcr     p15,0,R0,c1,c0,0
  82   bx      LR
  83
  84 ASM_PFX(ArmMmuEnabled):
  85   mrc     p15,0,R0,c1,c0,0
  86   and     R0,R0,#1
  87   bx      LR
  88
  89 ASM_PFX(ArmDisableMmu):
  90   mrc     p15,0,R0,c1,c0,0
  91   bic     R0,R0,#1
  92   mcr     p15,0,R0,c1,c0,0
  93   mov     R0,#0
  94   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
  95   mov     R0,#0
  96   mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
  97   bx      LR
  98
  99 ASM_PFX(ArmEnableDataCache):
 100   ldr     R1,=DC_ON
 101   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 102   orr     R0,R0,R1              @Set C bit
 103   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 104   bx      LR
 105
 106 ASM_PFX(ArmDisableDataCache):
 107   ldr     R1,=DC_ON
 108   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 109   bic     R0,R0,R1              @Clear C bit
 110   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 111   bx      LR
 112
 113 ASM_PFX(ArmEnableInstructionCache):
 114   ldr     R1,=IC_ON
 115   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 116   orr     R0,R0,R1             @Set I bit
 117   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 118   bx      LR
 119
 120 ASM_PFX(ArmDisableInstructionCache):
 121   ldr     R1,=IC_ON
 122   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 123   bic     R0,R0,R1             @Clear I bit.
 124   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 125   bx      LR
 126
 127 ASM_PFX(ArmEnableBranchPrediction):
 128   mrc     p15, 0, r0, c1, c0, 0
 129   orr     r0, r0, #0x00000800
 130   mcr     p15, 0, r0, c1, c0, 0
 131   bx      LR
 132
 133 ASM_PFX(ArmDisableBranchPrediction):
 134   mrc     p15, 0, r0, c1, c0, 0
 135   bic     r0, r0, #0x00000800
 136   mcr     p15, 0, r0, c1, c0, 0
 137   bx      LR
 138
 139 ASM_PFX(ArmDataMemoryBarrier):
 140   mov R0, #0
 141   mcr P15, #0, R0, C7, C10, #5
 142   bx      LR
 143
 144 ASM_PFX(ArmDataSyncronizationBarrier):
 145   mov R0, #0
 146   mcr P15, #0, R0, C7, C10, #4
 147   bx      LR
 148
 149 ASM_PFX(ArmInstructionSynchronizationBarrier):
 150   mov R0, #0
 151   mcr P15, #0, R0, C7, C5, #4
 152   bx      LR
 153
 154
 155 ASM_FUNCTION_REMOVE_IF_UNREFERENCED