ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17 .globl ASM_PFX(ArmCleanInvalidateDataCache)
  18 .globl ASM_PFX(ArmCleanDataCache)
  19 .globl ASM_PFX(ArmInvalidateDataCache)
  20 .globl ASM_PFX(ArmInvalidateInstructionCache)
  21 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
  22 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
  23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
  24 .globl ASM_PFX(ArmEnableMmu)
  25 .globl ASM_PFX(ArmDisableMmu)
  26 .globl ASM_PFX(ArmEnableDataCache)
  27 .globl ASM_PFX(ArmDisableDataCache)
  28 .globl ASM_PFX(ArmEnableInstructionCache)
  29 .globl ASM_PFX(ArmDisableInstructionCache)
  30 .globl ASM_PFX(ArmEnableBranchPrediction)
  31 .globl ASM_PFX(ArmDisableBranchPrediction)
  32
  33 .set DC_ON, (0x1<<2)
  34 .set IC_ON, (0x1<<12)
  35 .set XP_ON, (0x1<<23)
  36
  37 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  38   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  39   bx      lr
  40
  41
  42 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  43   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  44   bx      lr
  45
  46
  47 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  48   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  49   bx      lr
  50
  51
  52 ASM_PFX(ArmCleanDataCache):
  53   mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
  54   bx      lr
  55
  56
  57 ASM_PFX(ArmCleanInvalidateDataCache):
  58   mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
  59   bx      lr
  60
  61
  62 ASM_PFX(ArmInvalidateDataCache):
  63   mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
  64   bx      lr
  65
  66
  67 ASM_PFX(ArmInvalidateInstructionCache):
  68   mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
  69   mov     R0,#0
  70   mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
  71   bx      lr
  72
  73 ASM_PFX(ArmEnableMmu):
  74   mrc     p15,0,R0,c1,c0,0
  75   orr     R0,R0,#1
  76   mcr     p15,0,R0,c1,c0,0
  77   bx      LR
  78
  79 ASM_PFX(ArmDisableMmu):
  80   mrc     p15,0,R0,c1,c0,0
  81   bic     R0,R0,#1
  82   mcr     p15,0,R0,c1,c0,0
  83   mov     R0,#0
  84   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
  85   mov     R0,#0
  86   mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
  87   bx      LR
  88
  89 ASM_PFX(ArmEnableDataCache):
  90   ldr     R1,=DC_ON
  91   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  92   orr     R0,R0,R1              @Set C bit
  93   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
  94   bx      LR
  95
  96 ASM_PFX(ArmDisableDataCache):
  97   ldr     R1,=DC_ON
  98   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
  99   bic     R0,R0,R1              @Clear C bit
 100   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 101   bx      LR
 102
 103 ASM_PFX(ArmEnableInstructionCache):
 104   ldr     R1,=IC_ON
 105   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 106   orr     R0,R0,R1             @Set I bit
 107   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 108   bx      LR
 109
 110 ASM_PFX(ArmDisableInstructionCache):
 111   ldr     R1,=IC_ON
 112   mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
 113   bic     R0,R0,R1             @Clear I bit.
 114   mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
 115   bx      LR
 116
 117 ASM_PFX(ArmEnableBranchPrediction):
 118   mrc     p15, 0, r0, c1, c0, 0
 119   orr     r0, r0, #0x00000800
 120   mcr     p15, 0, r0, c1, c0, 0
 121   bx      LR
 122
 123 ASM_PFX(ArmDisableBranchPrediction):
 124   mrc     p15, 0, r0, c1, c0, 0
 125   bic     r0, r0, #0x00000800
 126   mcr     p15, 0, r0, c1, c0, 0
 127   bx      LR
 128
 129 ASM_FUNCTION_REMOVE_IF_UNREFERENCED