ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmCleanInvalidateDataCache
  16     EXPORT  ArmCleanDataCache
  17     EXPORT  ArmInvalidateDataCache
  18     EXPORT  ArmInvalidateInstructionCache
  19     EXPORT  ArmInvalidateDataCacheEntryByMVA
  20     EXPORT  ArmCleanDataCacheEntryByMVA
  21     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  22     EXPORT  ArmEnableMmu
  23     EXPORT  ArmDisableMmu
  24     EXPORT  ArmMmuEnabled
  25     EXPORT  ArmEnableDataCache
  26     EXPORT  ArmDisableDataCache
  27     EXPORT  ArmEnableInstructionCache
  28     EXPORT  ArmDisableInstructionCache
  29     EXPORT  ArmEnableBranchPrediction
  30     EXPORT  ArmDisableBranchPrediction
  31     EXPORT  ArmDataMemoryBarrier
  32     EXPORT  ArmDataSyncronizationBarrier
  33     EXPORT  ArmInstructionSynchronizationBarrier
  34
  35
  36 DC_ON       EQU     ( 0x1:SHL:2 )
  37 IC_ON       EQU     ( 0x1:SHL:12 )
  38 XP_ON       EQU     ( 0x1:SHL:23 )
  39
  40
  41     AREA    ArmCacheLib, CODE, READONLY
  42     PRESERVE8
  43
  44
  45 ArmInvalidateDataCacheEntryByMVA
  46   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  47   bx      lr
  48
  49
  50 ArmCleanDataCacheEntryByMVA
  51   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  52   bx      lr
  53
  54
  55 ArmCleanInvalidateDataCacheEntryByMVA
  56   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  57   bx      lr
  58
  59
  60 ArmCleanDataCache
  61   mcr     p15, 0, r0, c7, c10, 0  ; clean entire data cache
  62   bx      lr
  63
  64
  65 ArmCleanInvalidateDataCache
  66   mcr     p15, 0, r0, c7, c14, 0  ; clean and invalidate entire data cache
  67   bx      lr
  68
  69
  70 ArmInvalidateDataCache
  71   mcr     p15, 0, r0, c7, c6, 0  ; invalidate entire data cache
  72   bx      lr
  73
  74
  75 ArmInvalidateInstructionCache
  76   mcr     p15, 0, r0, c7, c5, 0  ;invalidate entire instruction cache
  77   mov     R0,#0
  78   mcr     p15,0,R0,c7,c5,4       ;Flush Prefetch buffer
  79   bx      lr
  80
  81 ArmEnableMmu
  82   mrc     p15,0,R0,c1,c0,0
  83   orr     R0,R0,#1
  84   mcr     p15,0,R0,c1,c0,0
  85   bx      LR
  86
  87 ArmMmuEnabled
  88   mrc     p15,0,R0,c1,c0,0
  89   and     R0,R0,#1
  90   bx      LR
  91
  92 ArmDisableMmu
  93   mrc     p15,0,R0,c1,c0,0
  94   bic     R0,R0,#1
  95   mcr     p15,0,R0,c1,c0,0
  96   mov     R0,#0
  97   mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
  98   mov     R0,#0
  99   mcr     p15,0,R0,c7,c5,4      ;Flush Prefetch buffer
 100   bx      LR
 101
 102 ArmEnableDataCache
 103   LDR     R1,=DC_ON
 104   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 105   ORR     R0,R0,R1              ;Set C bit
 106   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 107   BX      LR
 108
 109 ArmDisableDataCache
 110   LDR     R1,=DC_ON
 111   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 112   BIC     R0,R0,R1              ;Clear C bit
 113   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 114   BX      LR
 115
 116 ArmEnableInstructionCache
 117   LDR     R1,=IC_ON
 118   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
 119   ORR     R0,R0,R1             ;Set I bit
 120   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
 121   BX      LR
 122
 123 ArmDisableInstructionCache
 124   LDR     R1,=IC_ON
 125   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
 126   BIC     R0,R0,R1             ;Clear I bit.
 127   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
 128   BX      LR
 129
 130 ArmEnableBranchPrediction
 131   mrc     p15, 0, r0, c1, c0, 0
 132   orr     r0, r0, #0x00000800
 133   mcr     p15, 0, r0, c1, c0, 0
 134   bx      LR
 135
 136 ArmDisableBranchPrediction
 137   mrc     p15, 0, r0, c1, c0, 0
 138   bic     r0, r0, #0x00000800
 139   mcr     p15, 0, r0, c1, c0, 0
 140   bx      LR
 141
 142 ASM_PFX(ArmDataMemoryBarrier):
 143   mov R0, #0
 144   mcr P15, #0, R0, C7, C10, #5
 145   bx      LR
 146
 147 ASM_PFX(ArmDataSyncronizationBarrier):
 148   mov R0, #0
 149   mcr P15, #0, R0, C7, C10, #4
 150   bx      LR
 151
 152 ASM_PFX(ArmInstructionSynchronizationBarrier):
 153   MOV R0, #0
 154   MCR P15, #0, R0, C7, C5, #4
 155   bx      LR
 156
 157     END