1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
5 // This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmCleanInvalidateDataCache
16 EXPORT ArmCleanDataCache
17 EXPORT ArmInvalidateDataCache
18 EXPORT ArmInvalidateInstructionCache
19 EXPORT ArmInvalidateDataCacheEntryByMVA
20 EXPORT ArmCleanDataCacheEntryByMVA
21 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
25 EXPORT ArmEnableDataCache
26 EXPORT ArmDisableDataCache
27 EXPORT ArmEnableInstructionCache
28 EXPORT ArmDisableInstructionCache
29 EXPORT ArmEnableBranchPrediction
30 EXPORT ArmDisableBranchPrediction
31 EXPORT ArmDataMemoryBarrier
32 EXPORT ArmDataSyncronizationBarrier
33 EXPORT ArmInstructionSynchronizationBarrier
36 DC_ON EQU ( 0x1:SHL:2 )
37 IC_ON EQU ( 0x1:SHL:12 )
38 XP_ON EQU ( 0x1:SHL:23 )
41 AREA ArmCacheLib, CODE, READONLY
45 ArmInvalidateDataCacheEntryByMVA
46 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
50 ArmCleanDataCacheEntryByMVA
51 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
55 ArmCleanInvalidateDataCacheEntryByMVA
56 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
61 mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache
65 ArmCleanInvalidateDataCache
66 mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache
70 ArmInvalidateDataCache
71 mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache
75 ArmInvalidateInstructionCache
76 mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache
78 mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
97 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
99 mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer
104 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
105 ORR R0,R0,R1 ;Set C bit
106 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
111 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
112 BIC R0,R0,R1 ;Clear C bit
113 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
116 ArmEnableInstructionCache
118 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
119 ORR R0,R0,R1 ;Set I bit
120 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
123 ArmDisableInstructionCache
125 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
126 BIC R0,R0,R1 ;Clear I bit.
127 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
130 ArmEnableBranchPrediction
131 mrc p15, 0, r0, c1, c0, 0
132 orr r0, r0, #0x00000800
133 mcr p15, 0, r0, c1, c0, 0
136 ArmDisableBranchPrediction
137 mrc p15, 0, r0, c1, c0, 0
138 bic r0, r0, #0x00000800
139 mcr p15, 0, r0, c1, c0, 0
142 ASM_PFX(ArmDataMemoryBarrier):
144 mcr P15, #0, R0, C7, C10, #5
147 ASM_PFX(ArmDataSyncronizationBarrier):
149 mcr P15, #0, R0, C7, C10, #4
152 ASM_PFX(ArmInstructionSynchronizationBarrier):
154 MCR P15, #0, R0, C7, C5, #4