ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include <Chipset/ARM926EJ-S.h>
  16 #include <Library/ArmLib.h>
  17 #include <Library/BaseMemoryLib.h>
  18 #include <Library/MemoryAllocationLib.h>
  19 #include <Library/DebugLib.h>
  20
  21 VOID
  22 FillTranslationTable (
  23   IN  UINT32                        *TranslationTable,
  24   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
  25   )
  26 {
  27   UINT32  *Entry;
  28   UINTN   Sections;
  29   UINTN   Index;
  30   UINT32  Attributes;
  31   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
  32
  33   switch (MemoryRegion->Attributes) {
  34     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
  35       Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
  36       break;
  37     case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
  38       Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
  39       break;
  40     case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
  41       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
  42       break;
  43     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
  44     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
  45     case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
  46       ASSERT(0); // Trustzone is not supported on ARMv5
  47     default:
  48       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
  49       break;
  50   }
  51
  52   Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
  53   Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
  54
  55   // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary
  56   ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);
  57
  58   for (Index = 0; Index < Sections; Index++)
  59   {
  60     *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
  61     PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
  62   }
  63 }
  64
  65 VOID
  66 EFIAPI
  67 ArmConfigureMmu (
  68   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
  69   OUT VOID                          **TranslationTableBase OPTIONAL,
  70   OUT UINTN                         *TranslationTableSize  OPTIONAL
  71   )
  72 {
  73   VOID  *TranslationTable;
  74
  75   // Allocate pages for translation table.
  76   TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
  77   TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
  78
  79   if (TranslationTableBase != NULL) {
  80     *TranslationTableBase = TranslationTable;
  81   }
  82
  83   if (TranslationTableBase != NULL) {
  84     *TranslationTableSize = TRANSLATION_TABLE_SIZE;
  85   }
  86
  87   ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
  88
  89   ArmCleanInvalidateDataCache();
  90   ArmInvalidateInstructionCache();
  91   ArmInvalidateTlb();
  92
  93   ArmDisableDataCache();
  94   ArmDisableInstructionCache();
  95   ArmDisableMmu();
  96
  97   // Make sure nothing sneaked into the cache
  98   ArmCleanInvalidateDataCache();
  99   ArmInvalidateInstructionCache();
 100
 101   while (MemoryTable->Length != 0) {
 102     FillTranslationTable(TranslationTable, MemoryTable);
 103     MemoryTable++;
 104   }
 105
 106   ArmSetTTBR0(TranslationTable);
 107
 108   ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
 109                             DOMAIN_ACCESS_CONTROL_NONE(14) |
 110                             DOMAIN_ACCESS_CONTROL_NONE(13) |
 111                             DOMAIN_ACCESS_CONTROL_NONE(12) |
 112                             DOMAIN_ACCESS_CONTROL_NONE(11) |
 113                             DOMAIN_ACCESS_CONTROL_NONE(10) |
 114                             DOMAIN_ACCESS_CONTROL_NONE( 9) |
 115                             DOMAIN_ACCESS_CONTROL_NONE( 8) |
 116                             DOMAIN_ACCESS_CONTROL_NONE( 7) |
 117                             DOMAIN_ACCESS_CONTROL_NONE( 6) |
 118                             DOMAIN_ACCESS_CONTROL_NONE( 5) |
 119                             DOMAIN_ACCESS_CONTROL_NONE( 4) |
 120                             DOMAIN_ACCESS_CONTROL_NONE( 3) |
 121                             DOMAIN_ACCESS_CONTROL_NONE( 2) |
 122                             DOMAIN_ACCESS_CONTROL_NONE( 1) |
 123                             DOMAIN_ACCESS_CONTROL_MANAGER(0));
 124
 125   ArmEnableInstructionCache();
 126   ArmEnableDataCache();
 127   ArmEnableMmu();
 128 }
 129
 130
 131