1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 # All rights reserved. This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
17 .globl ASM_PFX(ArmCleanInvalidateDataCache)
18 .globl ASM_PFX(ArmCleanDataCache)
19 .globl ASM_PFX(ArmInvalidateDataCache)
20 .globl ASM_PFX(ArmInvalidateInstructionCache)
21 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
22 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
24 .globl ASM_PFX(ArmEnableMmu)
25 .globl ASM_PFX(ArmDisableMmu)
26 .globl ASM_PFX(ArmEnableDataCache)
27 .globl ASM_PFX(ArmDisableDataCache)
28 .globl ASM_PFX(ArmEnableInstructionCache)
29 .globl ASM_PFX(ArmDisableInstructionCache)
30 .globl ASM_PFX(ArmEnableBranchPrediction)
31 .globl ASM_PFX(ArmDisableBranchPrediction)
36 #------------------------------------------------------------------------------
38 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
39 mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line
42 ASM_PFX(ArmCleanDataCacheEntryByMVA):
43 mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line
46 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
47 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line
50 ASM_PFX(ArmEnableInstructionCache):
52 mrc p15,0,r0,c1,c0,0 @Read control register configuration data
53 orr r0,r0,r1 @Set I bit
54 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
57 ASM_PFX(ArmDisableInstructionCache):
59 mrc p15,0,r0,c1,c0,0 @Read control register configuration data
60 bic r0,r0,r1 @Clear I bit.
61 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
64 ASM_PFX(ArmInvalidateInstructionCache):
66 mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.
67 @Also flushes the branch target cache.
69 mcr p15,0,r0,c7,c10,4 @Data write buffer
72 ASM_PFX(ArmEnableMmu):
78 ASM_PFX(ArmDisableMmu):
83 mcr p15,0,R0,c7,c10,4 @Drain write buffer
86 ASM_PFX(ArmEnableDataCache):
88 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
89 orr R0,R0,R1 @Set C bit
90 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
93 ASM_PFX(ArmDisableDataCache):
95 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
96 bic R0,R0,R1 @Clear C bit
97 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
100 ASM_PFX(ArmCleanDataCache):
101 mrc p15,0,r15,c7,c10,3
102 bne ASM_PFX(ArmCleanDataCache)
104 mcr p15,0,R0,c7,c10,4 @Drain write buffer
107 ASM_PFX(ArmInvalidateDataCache):
109 mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache
111 mcr p15,0,R0,c7,c10,4 @Drain write buffer
114 ASM_PFX(ArmCleanInvalidateDataCache):
115 mrc p15,0,r15,c7,c14,3
116 bne ASM_PFX(ArmCleanInvalidateDataCache)
118 mcr p15,0,R0,c7,c10,4 @Drain write buffer
121 ASM_PFX(ArmEnableBranchPrediction):
122 bx LR @Branch prediction is not supported.
124 ASM_PFX(ArmDisableBranchPrediction):
125 bx LR @Branch prediction is not supported.
127 ASM_FUNCTION_REMOVE_IF_UNREFERENCED