1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmCleanInvalidateDataCache
16 EXPORT ArmCleanDataCache
17 EXPORT ArmInvalidateDataCache
18 EXPORT ArmInvalidateInstructionCache
19 EXPORT ArmInvalidateDataCacheEntryByMVA
20 EXPORT ArmCleanDataCacheEntryByMVA
21 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
25 EXPORT ArmEnableDataCache
26 EXPORT ArmDisableDataCache
27 EXPORT ArmEnableInstructionCache
28 EXPORT ArmDisableInstructionCache
29 EXPORT ArmEnableBranchPrediction
30 EXPORT ArmDisableBranchPrediction
31 EXPORT ArmDataMemoryBarrier
32 EXPORT ArmDataSyncronizationBarrier
33 EXPORT ArmInstructionSynchronizationBarrier
36 DC_ON EQU ( 0x1:SHL:2 )
37 IC_ON EQU ( 0x1:SHL:12 )
39 AREA ArmCacheLib, CODE, READONLY
43 ArmInvalidateDataCacheEntryByMVA
44 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
48 ArmCleanDataCacheEntryByMVA
49 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
53 ArmCleanInvalidateDataCacheEntryByMVA
54 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
57 ArmEnableInstructionCache
59 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
60 ORR R0,R0,R1 ;Set I bit
61 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
64 ArmDisableInstructionCache
66 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
67 BIC R0,R0,R1 ;Clear I bit.
68 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
71 ArmInvalidateInstructionCache
73 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
75 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
94 mcr p15,0,R0,c7,c10,4 ;Drain write buffer
99 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
100 ORR R0,R0,R1 ;Set C bit
101 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
106 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
107 BIC R0,R0,R1 ;Clear C bit
108 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
112 MRC p15,0,r15,c7,c10,3
113 BNE ArmCleanDataCache
115 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
118 ArmInvalidateDataCache
120 MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache
122 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
125 ArmCleanInvalidateDataCache
126 MRC p15,0,r15,c7,c14,3
127 BNE ArmCleanInvalidateDataCache
129 MCR p15,0,R0,c7,c10,4 ;Drain write buffer
132 ArmEnableBranchPrediction
133 bx LR ;Branch prediction is not supported.
135 ArmDisableBranchPrediction
136 bx LR ;Branch prediction is not supported.
138 ASM_PFX(ArmDataMemoryBarrier):
140 mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct
143 ASM_PFX(ArmDataSyncronizationBarrier):
145 mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct
148 ASM_PFX(ArmInstructionSynchronizationBarrier):
150 MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct