3 Copyright (c) 2008-2009, Apple Inc. All rights reserved.
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Chipset/Cortex-A8.h>
16 #include <Library/ArmLib.h>
17 #include <Library/BaseLib.h>
18 #include <Library/BaseMemoryLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include "ArmCortexALib.h"
23 FillTranslationTable (
24 IN UINT32
*TranslationTable
,
25 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryRegion
32 UINT32 PhysicalBase
= MemoryRegion
->PhysicalBase
;
34 switch (MemoryRegion
->Attributes
) {
35 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
:
36 Attributes
= TT_DESCRIPTOR_SECTION_WRITE_BACK
;
38 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
:
39 Attributes
= TT_DESCRIPTOR_SECTION_WRITE_THROUGH
;
41 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
:
42 Attributes
= TT_DESCRIPTOR_SECTION_DEVICE
;
44 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
:
46 Attributes
= TT_DESCRIPTOR_SECTION_UNCACHED
;
50 Entry
= TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable
, MemoryRegion
->VirtualBase
);
51 Sections
= MemoryRegion
->Length
/ TT_DESCRIPTOR_SECTION_SIZE
;
53 for (Index
= 0; Index
< Sections
; Index
++)
55 *Entry
++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase
) | Attributes
;
56 PhysicalBase
+= TT_DESCRIPTOR_SECTION_SIZE
;
63 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
64 OUT VOID
**TranslationTableBase OPTIONAL
,
65 OUT UINTN
*TranslationTableSize OPTIONAL
68 VOID
*TranslationTable
;
70 // Allocate pages for translation table.
71 TranslationTable
= AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE
+ TRANSLATION_TABLE_ALIGNMENT
));
72 TranslationTable
= (VOID
*)(((UINTN
)TranslationTable
+ TRANSLATION_TABLE_ALIGNMENT_MASK
) & ~TRANSLATION_TABLE_ALIGNMENT_MASK
);
74 if (TranslationTableBase
!= NULL
) {
75 *TranslationTableBase
= TranslationTable
;
78 if (TranslationTableBase
!= NULL
) {
79 *TranslationTableSize
= TRANSLATION_TABLE_SIZE
;
82 ZeroMem(TranslationTable
, TRANSLATION_TABLE_SIZE
);
84 ArmCleanInvalidateDataCache();
85 ArmInvalidateInstructionCache();
88 ArmDisableDataCache();
89 ArmDisableInstructionCache();
92 // Make sure nothing sneaked into the cache
93 ArmCleanInvalidateDataCache();
94 ArmInvalidateInstructionCache();
96 while (MemoryTable
->Length
!= 0) {
97 FillTranslationTable(TranslationTable
, MemoryTable
);
101 ArmSetTranslationTableBaseAddress(TranslationTable
);
103 ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
104 DOMAIN_ACCESS_CONTROL_NONE(14) |
105 DOMAIN_ACCESS_CONTROL_NONE(13) |
106 DOMAIN_ACCESS_CONTROL_NONE(12) |
107 DOMAIN_ACCESS_CONTROL_NONE(11) |
108 DOMAIN_ACCESS_CONTROL_NONE(10) |
109 DOMAIN_ACCESS_CONTROL_NONE( 9) |
110 DOMAIN_ACCESS_CONTROL_NONE( 8) |
111 DOMAIN_ACCESS_CONTROL_NONE( 7) |
112 DOMAIN_ACCESS_CONTROL_NONE( 6) |
113 DOMAIN_ACCESS_CONTROL_NONE( 5) |
114 DOMAIN_ACCESS_CONTROL_NONE( 4) |
115 DOMAIN_ACCESS_CONTROL_NONE( 3) |
116 DOMAIN_ACCESS_CONTROL_NONE( 2) |
117 DOMAIN_ACCESS_CONTROL_NONE( 1) |
118 DOMAIN_ACCESS_CONTROL_MANAGER(0));
120 ArmEnableInstructionCache();
121 ArmEnableDataCache();
131 return ARM_CACHE_TYPE_WRITE_BACK
;
134 ARM_CACHE_ARCHITECTURE
136 ArmCacheArchitecture (
140 return ARM_CACHE_ARCHITECTURE_SEPARATE
;
145 ArmDataCachePresent (
163 ArmDataCacheAssociativity (
180 ArmDataCacheLineLength (
189 ArmInstructionCachePresent (
198 ArmInstructionCacheSize (
207 ArmInstructionCacheAssociativity (
216 ArmInstructionCacheLineLength (
224 ArmCortexADataCacheOperation (
225 IN ARM_CORTEX_A_CACHE_OPERATION DataCacheOperation
235 UINTN SavedInterruptState
;
237 SetCount
= ArmDataCacheSets();
238 WayCount
= ArmDataCacheAssociativity();
240 // Cortex-A8 Manual, System Control Coprocessor chapter
242 WayShift
= 32 - LowBitSet32 ((UINT32
)WayCount
);
244 SavedInterruptState
= ArmDisableInterrupts();
246 for (Way
= 0; Way
< WayCount
; Way
++) {
247 for (Set
= 0; Set
< SetCount
; Set
++) {
248 // Build the format that the CP15 instruction can understand
249 SetWayFormat
= (Way
<< WayShift
) | (Set
<< SetShift
);
252 (*DataCacheOperation
)(SetWayFormat
);
256 ArmDrainWriteBuffer();
258 if (SavedInterruptState
) {
259 ArmEnableInterrupts();
265 ArmInvalidateDataCache (
269 ArmCortexADataCacheOperation(ArmInvalidateDataCacheEntryBySetWay
);
274 ArmCleanInvalidateDataCache (
278 ArmCortexADataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay
);
287 ArmCortexADataCacheOperation(ArmCleanDataCacheEntryBySetWay
);