ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17 .globl ASM_PFX(ArmInvalidateInstructionCache)
  18 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
  19 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
  20 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
  21 .globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
  22 .globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
  23 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
  24 .globl ASM_PFX(ArmDrainWriteBuffer)
  25 .globl ASM_PFX(ArmEnableMmu)
  26 .globl ASM_PFX(ArmDisableMmu)
  27 .globl ASM_PFX(ArmMmuEnabled)
  28 .globl ASM_PFX(ArmEnableDataCache)
  29 .globl ASM_PFX(ArmDisableDataCache)
  30 .globl ASM_PFX(ArmEnableInstructionCache)
  31 .globl ASM_PFX(ArmDisableInstructionCache)
  32 .globl ASM_PFX(ArmEnableExtendPTConfig)
  33 .globl ASM_PFX(ArmDisableExtendPTConfig)
  34 .globl ASM_PFX(ArmEnableBranchPrediction)
  35 .globl ASM_PFX(ArmDisableBranchPrediction)
  36
  37 .set DC_ON, (0x1<<2)
  38 .set IC_ON, (0x1<<12)
  39 .set XP_ON, (0x1<<23)
  40
  41 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  42   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  43   bx      lr
  44
  45
  46 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  47   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  48   bx      lr
  49
  50
  51 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  52   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  53   bx      lr
  54
  55
  56 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  57   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  58   bx      lr
  59
  60
  61 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  62   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  63   bx      lr
  64
  65
  66 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  67   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  68   bx      lr
  69
  70
  71 ASM_PFX(ArmDrainWriteBuffer):
  72   mcr     p15, 0, r0, c7, c10, 4       @ Drain write buffer for sync
  73   bx      lr
  74
  75
  76 ASM_PFX(ArmInvalidateInstructionCache):
  77   mov     R0,#0
  78   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  79   mov     R0,#0
  80   mcr     p15,0,R0,c7,c5,4      @Instruction synchronization barrier
  81   bx      LR
  82
  83 ASM_PFX(ArmEnableMmu):
  84   mrc     p15,0,R0,c1,c0,0
  85   orr     R0,R0,#1
  86   mcr     p15,0,R0,c1,c0,0
  87   bx      LR
  88
  89 ASM_PFX(ArmMmuEnabled):
  90   mrc     p15,0,R0,c1,c0,0
  91   and     R0,R0,#1
  92   bx      LR
  93
  94
  95 ASM_PFX(ArmDisableMmu):
  96   mov     R0,#0
  97   mcr     p15,0,R0,c13,c0,0     @FCSE PID register must be cleared before disabling MMU
  98   mrc     p15,0,R0,c1,c0,0
  99   bic     R0,R0,#1
 100   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 101   mov     R0,#0
 102   mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
 103   mov     R0,#0
 104   mcr     p15,0,R0,c7,c5,4      @Instruction synchronization barrier
 105   bx      LR
 106
 107 ASM_PFX(ArmEnableDataCache):
 108   ldr     R1,=DC_ON
 109   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 110   orr     R0,R0,R1              @Set C bit
 111   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 112   bx      LR
 113
 114 ASM_PFX(ArmDisableDataCache):
 115   ldr     R1,=DC_ON
 116   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 117   bic     R0,R0,R1              @Clear C bit
 118   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 119   bx      LR
 120
 121 ASM_PFX(ArmEnableInstructionCache):
 122   ldr     R1,=IC_ON
 123   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 124   orr     R0,R0,R1              @Set I bit
 125   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 126   bx      LR
 127
 128 ASM_PFX(ArmDisableInstructionCache):
 129   ldr     R1,=IC_ON
 130   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 131   bic     R0,R0,R1              @Clear I bit.
 132   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 133   bx      LR
 134
 135 ASM_PFX(ArmEnableBranchPrediction):
 136   mrc     p15, 0, r0, c1, c0, 0
 137   orr     r0, r0, #0x00000800
 138   mcr     p15, 0, r0, c1, c0, 0
 139   bx      LR
 140
 141 ASM_PFX(ArmDisableBranchPrediction):
 142   mrc     p15, 0, r0, c1, c0, 0
 143   bic     r0, r0, #0x00000800
 144   mcr     p15, 0, r0, c1, c0, 0
 145   bx      LR
 146
 147 ASM_FUNCTION_REMOVE_IF_UNREFERENCED