]> git.proxmox.com Git - mirror_edk2.git/blob - ArmPkg/Library/ArmLib/ArmLibPrivate.h
UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmLibPrivate.h
1 /** @file
2 ArmLibPrivate.h
3
4 Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
5 Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
6
7 SPDX-License-Identifier: BSD-2-Clause-Patent
8
9 **/
10
11 #ifndef ARM_LIB_PRIVATE_H_
12 #define ARM_LIB_PRIVATE_H_
13
14 #define CACHE_SIZE_4_KB (3UL)
15 #define CACHE_SIZE_8_KB (4UL)
16 #define CACHE_SIZE_16_KB (5UL)
17 #define CACHE_SIZE_32_KB (6UL)
18 #define CACHE_SIZE_64_KB (7UL)
19 #define CACHE_SIZE_128_KB (8UL)
20
21 #define CACHE_ASSOCIATIVITY_DIRECT (0UL)
22 #define CACHE_ASSOCIATIVITY_4_WAY (2UL)
23 #define CACHE_ASSOCIATIVITY_8_WAY (3UL)
24
25 #define CACHE_PRESENT (0UL)
26 #define CACHE_NOT_PRESENT (1UL)
27
28 #define CACHE_LINE_LENGTH_32_BYTES (2UL)
29
30 #define SIZE_FIELD_TO_CACHE_SIZE(x) (((x) >> 6) & 0x0F)
31 #define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x) (((x) >> 3) & 0x07)
32 #define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
33 #define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
34
35 #define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
36 #define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
37
38 #define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
39 #define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
40 #define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
41 #define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
42
43 #define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
44 #define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
45 #define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
46 #define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
47
48 #define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
49 #define CACHE_TYPE_WRITE_BACK (0x0EUL)
50
51 #define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
52 #define CACHE_ARCHITECTURE_UNIFIED (0UL)
53 #define CACHE_ARCHITECTURE_SEPARATE (1UL)
54
55 VOID
56 CPSRMaskInsert (
57 IN UINT32 Mask,
58 IN UINT32 Value
59 );
60
61 UINT32
62 CPSRRead (
63 VOID
64 );
65
66 #endif // ARM_LIB_PRIVATE_H_