1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008-2010 Apple Inc. All rights reserved.
5 # All rights reserved. This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
15 .globl ASM_PFX(Cp15IdCode)
16 .globl ASM_PFX(Cp15CacheInfo)
17 .globl ASM_PFX(ArmEnableInterrupts)
18 .globl ASM_PFX(ArmDisableInterrupts)
19 .globl ASM_PFX(ArmGetInterruptState)
20 .globl ASM_PFX(ArmEnableFiq)
21 .globl ASM_PFX(ArmDisableFiq)
22 .globl ASM_PFX(ArmGetFiqState)
23 .globl ASM_PFX(ArmInvalidateTlb)
24 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
25 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
26 .globl ASM_PFX(ArmSetDomainAccessControl)
27 .globl ASM_PFX(ArmUpdateTranslationTableEntry)
28 .globl ASM_PFX(CPSRMaskInsert)
29 .globl ASM_PFX(CPSRRead)
30 .globl ASM_PFX(ReadCCSIDR)
31 .globl ASM_PFX(ReadCLIDR)
36 #------------------------------------------------------------------------------
42 ASM_PFX(Cp15CacheInfo):
46 ASM_PFX(ArmEnableInterrupts):
50 ASM_PFX(ArmDisableInterrupts):
54 ASM_PFX(ArmGetInterruptState):
56 tst R0,#0x80 @Check if IRQ is enabled.
61 ASM_PFX(ArmEnableFiq):
65 ASM_PFX(ArmDisableFiq):
69 ASM_PFX(ArmGetFiqState):
71 tst R0,#0x40 @Check if FIQ is enabled.
76 ASM_PFX(ArmInvalidateTlb):
79 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
84 ASM_PFX(ArmSetTranslationTableBaseAddress):
89 ASM_PFX(ArmGetTranslationTableBaseAddress):
95 ASM_PFX(ArmSetDomainAccessControl):
102 //ArmUpdateTranslationTableEntry (
103 // IN VOID *TranslationTableEntry // R0
104 // IN VOID *MVA // R1
106 ASM_PFX(ArmUpdateTranslationTableEntry):
107 mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
109 mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
110 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
115 ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
116 stmfd sp!, {r4-r12, lr} @ save all the banked registers
117 mov r3, sp @ copy the stack pointer into a non-banked register
118 mrs r2, cpsr @ read the cpsr
119 bic r2, r2, r0 @ clear mask in the cpsr
120 and r1, r1, r0 @ clear bits outside the mask in the input
121 orr r2, r2, r1 @ set field
122 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
124 mov sp, r3 @ restore stack pointer
125 ldmfd sp!, {r4-r12, lr} @ restore registers
126 bx lr @ return (hopefully thumb-safe!)
137 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
139 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
147 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
150 ASM_FUNCTION_REMOVE_IF_UNREFERENCED