1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
18 EXPORT ArmEnableInterrupts
19 EXPORT ArmDisableInterrupts
20 EXPORT ArmGetInterruptState
21 EXPORT ArmInvalidateTlb
22 EXPORT ArmSetTranslationTableBaseAddress
23 EXPORT ArmGetTranslationTableBaseAddress
24 EXPORT ArmSetDomainAccessControl
29 AREA ArmLibSupport, CODE, READONLY
49 tst R0,#0x80 ;Check if IRQ is enabled.
60 ArmSetTranslationTableBaseAddress
65 ArmGetTranslationTableBaseAddress
70 ArmSetDomainAccessControl
75 CPSRMaskInsert ; on entry, r0 is the mask and r1 is the field to insert
76 stmfd sp!, {r4-r12, lr} ; save all the banked registers
77 mov r3, sp ; copy the stack pointer into a non-banked register
78 mrs r2, cpsr ; read the cpsr
79 bic r2, r2, r0 ; clear mask in the cpsr
80 and r1, r1, r0 ; clear bits outside the mask in the input
81 orr r2, r2, r1 ; set field
82 msr cpsr_cxsf, r2 ; write back cpsr (may have caused a mode switch)
84 mov sp, r3 ; restore stack pointer
85 ldmfd sp!, {r4-r12, lr} ; restore registers
86 bx lr ; return (hopefully thumb-safe!)
98 MCR p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
100 MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
109 MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register