ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  Cp15IdCode
  17     EXPORT  Cp15CacheInfo
  18     EXPORT  ArmEnableInterrupts
  19     EXPORT  ArmDisableInterrupts
  20     EXPORT  ArmGetInterruptState
  21     EXPORT  ArmInvalidateTlb
  22     EXPORT  ArmSetTranslationTableBaseAddress
  23     EXPORT  ArmGetTranslationTableBaseAddress
  24     EXPORT  ArmSetDomainAccessControl
  25     EXPORT  CPSRMaskInsert
  26     EXPORT  CPSRRead
  27     EXPORT  ReadCCSIDR
  28
  29     AREA ArmLibSupport, CODE, READONLY
  30
  31 Cp15IdCode
  32   mrc     p15,0,R0,c0,c0,0
  33   bx      LR
  34
  35 Cp15CacheInfo
  36   mrc     p15,0,R0,c0,c0,1
  37   bx      LR
  38
  39 ArmEnableInterrupts
  40   CPSIE   i
  41         bx      LR
  42
  43 ArmDisableInterrupts
  44   CPSID   i
  45         bx      LR
  46
  47 ArmGetInterruptState
  48         mrs     R0,CPSR
  49         tst     R0,#0x80            ;Check if IRQ is enabled.
  50         moveq   R0,#1
  51         movne   R0,#0
  52         bx      LR
  53
  54 ArmInvalidateTlb
  55   mov     r0,#0
  56   mcr     p15,0,r0,c8,c7,0
  57   ISB
  58   bx      lr
  59
  60 ArmSetTranslationTableBaseAddress
  61   mcr     p15,0,r0,c2,c0,0
  62   ISB
  63   bx      lr
  64
  65 ArmGetTranslationTableBaseAddress
  66   mrc     p15,0,r0,c2,c0,0
  67   ISB
  68   bx      lr
  69
  70 ArmSetDomainAccessControl
  71   mcr     p15,0,r0,c3,c0,0
  72   ISB
  73   bx      lr
  74
  75 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
  76   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
  77   mov     r3, sp            ; copy the stack pointer into a non-banked register
  78   mrs     r2, cpsr          ; read the cpsr
  79   bic     r2, r2, r0        ; clear mask in the cpsr
  80   and     r1, r1, r0        ; clear bits outside the mask in the input
  81   orr     r2, r2, r1        ; set field
  82   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
  83   ISB
  84   mov     sp, r3            ; restore stack pointer
  85   ldmfd   sp!, {r4-r12, lr} ; restore registers
  86   bx      lr                ; return (hopefully thumb-safe!)
  87
  88 CPSRRead
  89   mrs     r0, cpsr
  90   bx      lr
  91
  92
  93 // UINT32
  94 // ReadCCSIDR (
  95 //   IN UINT32 CSSELR
  96 //   )
  97 ReadCCSIDR
  98   MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  99   ISB
 100   MRC p15,1,<Rt>,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
 101   BX  lr
 102
 103
 104 // UINT32
 105 // ReadCLIDR (
 106 //   IN UINT32 CSSELR
 107 //   )
 108 ReadCLIDR
 109   MRC p15,1,<Rt>,c0,c0,1 ; Read CP15 Cache Level ID Register
 110   END
 111
 112