ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  Cp15IdCode
  17     EXPORT  Cp15CacheInfo
  18     EXPORT  ArmEnableInterrupts
  19     EXPORT  ArmDisableInterrupts
  20     EXPORT  ArmGetInterruptState
  21     EXPORT  ArmEnableFiq
  22     EXPORT  ArmDisableFiq
  23     EXPORT  ArmGetFiqState
  24     EXPORT  ArmInvalidateTlb
  25     EXPORT  ArmSetTranslationTableBaseAddress
  26     EXPORT  ArmGetTranslationTableBaseAddress
  27     EXPORT  ArmSetDomainAccessControl
  28     EXPORT  CPSRMaskInsert
  29     EXPORT  CPSRRead
  30     EXPORT  ReadCCSIDR
  31     EXPORT  ReadCLIDR
  32
  33     AREA ArmLibSupport, CODE, READONLY
  34
  35 Cp15IdCode
  36   mrc     p15,0,R0,c0,c0,0
  37   bx      LR
  38
  39 Cp15CacheInfo
  40   mrc     p15,0,R0,c0,c0,1
  41   bx      LR
  42
  43 ArmEnableInterrupts
  44   CPSIE   i
  45         bx      LR
  46
  47 ArmDisableInterrupts
  48   CPSID   i
  49         bx      LR
  50
  51 ArmGetInterruptState
  52         mrs     R0,CPSR
  53         tst     R0,#0x80            ;Check if IRQ is enabled.
  54         moveq   R0,#1
  55         movne   R0,#0
  56         bx      LR
  57
  58 ArmEnableFiq
  59   CPSIE   f
  60         bx      LR
  61
  62 ArmDisableFiq
  63   CPSID   f
  64         bx      LR
  65
  66 ArmGetFiqState
  67         mrs     R0,CPSR
  68         tst     R0,#0x40            ;Check if IRQ is enabled.
  69         moveq   R0,#1
  70         movne   R0,#0
  71         bx      LR
  72
  73 ArmInvalidateTlb
  74   mov     r0,#0
  75   mcr     p15,0,r0,c8,c7,0
  76   ISB
  77   bx      lr
  78
  79 ArmSetTranslationTableBaseAddress
  80   mcr     p15,0,r0,c2,c0,0
  81   ISB
  82   bx      lr
  83
  84 ArmGetTranslationTableBaseAddress
  85   mrc     p15,0,r0,c2,c0,0
  86   ISB
  87   bx      lr
  88
  89 ArmSetDomainAccessControl
  90   mcr     p15,0,r0,c3,c0,0
  91   ISB
  92   bx      lr
  93
  94 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
  95   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
  96   mov     r3, sp            ; copy the stack pointer into a non-banked register
  97   mrs     r2, cpsr          ; read the cpsr
  98   bic     r2, r2, r0        ; clear mask in the cpsr
  99   and     r1, r1, r0        ; clear bits outside the mask in the input
 100   orr     r2, r2, r1        ; set field
 101   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
 102   ISB
 103   mov     sp, r3            ; restore stack pointer
 104   ldmfd   sp!, {r4-r12, lr} ; restore registers
 105   bx      lr                ; return (hopefully thumb-safe!)
 106
 107 CPSRRead
 108   mrs     r0, cpsr
 109   bx      lr
 110
 111
 112 // UINT32
 113 // ReadCCSIDR (
 114 //   IN UINT32 CSSELR
 115 //   )
 116 ReadCCSIDR
 117   MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
 118   ISB
 119   MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
 120   BX  lr
 121
 122
 123 // UINT32
 124 // ReadCLIDR (
 125 //   IN UINT32 CSSELR
 126 //   )
 127 ReadCLIDR
 128   MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
 129   END
 130
 131