ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 //
   5 // This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  Cp15IdCode
  17     EXPORT  Cp15CacheInfo
  18     EXPORT  ArmIsMPCore
  19     EXPORT  ArmEnableAsynchronousAbort
  20     EXPORT  ArmDisableAsynchronousAbort
  21     EXPORT  ArmEnableIrq
  22     EXPORT  ArmDisableIrq
  23     EXPORT  ArmGetInterruptState
  24     EXPORT  ArmEnableFiq
  25     EXPORT  ArmDisableFiq
  26     EXPORT  ArmEnableInterrupts
  27     EXPORT  ArmDisableInterrupts
  28     EXPORT  ArmGetFiqState
  29     EXPORT  ArmInvalidateTlb
  30     EXPORT  ArmSetTTBR0
  31     EXPORT  ArmGetTTBR0BaseAddress
  32     EXPORT  ArmSetDomainAccessControl
  33     EXPORT  ArmUpdateTranslationTableEntry
  34     EXPORT  CPSRMaskInsert
  35     EXPORT  CPSRRead
  36     EXPORT  ReadCCSIDR
  37     EXPORT  ReadCLIDR
  38
  39     AREA ArmLibSupport, CODE, READONLY
  40
  41
  42 //------------------------------------------------------------------------------
  43
  44 Cp15IdCode
  45   mrc     p15,0,R0,c0,c0,0
  46   bx      LR
  47
  48 Cp15CacheInfo
  49   mrc     p15,0,R0,c0,c0,1
  50   bx      LR
  51
  52 ArmIsMPCore
  53   mrc     p15,0,R0,c0,c0,5
  54   // Get Multiprocessing extension (bit31) & U bit (bit30)
  55   and     R0, R0, #0xC0000000
  56   // if bit30 == 0 then the processor is part of a multiprocessor system)
  57   and     R0, R0, #0x80000000
  58   bx      LR
  59
  60 ArmEnableAsynchronousAbort
  61   cpsie   a
  62   isb
  63   bx      LR
  64
  65 ArmDisableAsynchronousAbort
  66   cpsid   a
  67   isb
  68   bx      LR
  69
  70 ArmEnableIrq
  71   cpsie   i
  72   isb
  73         bx      LR
  74
  75 ArmDisableIrq
  76   cpsid   i
  77   isb
  78         bx      LR
  79
  80 ArmEnableFiq
  81   cpsie   f
  82   isb
  83         bx      LR
  84
  85 ArmDisableFiq
  86   cpsid   f
  87   isb
  88   bx      LR
  89
  90 ArmEnableInterrupts
  91   cpsie   if
  92   isb
  93   bx      LR
  94
  95 ArmDisableInterrupts
  96   cpsid   if
  97   isb
  98   bx      LR
  99
 100 ArmGetInterruptState
 101   mrs     R0,CPSR
 102   tst     R0,#0x80          ;Check if IRQ is enabled.
 103   moveq   R0,#1
 104   movne   R0,#0
 105         bx      LR
 106
 107 ArmGetFiqState
 108         mrs     R0,CPSR
 109         tst     R0,#0x40            ;Check if FIQ is enabled.
 110         moveq   R0,#1
 111         movne   R0,#0
 112         bx      LR
 113
 114 ArmInvalidateTlb
 115   mov     r0,#0
 116   mcr     p15,0,r0,c8,c7,0
 117   mcr     p15,0,R9,c7,c5,6      ; BPIALL Invalidate Branch predictor array. R9 == NoOp
 118   dsb
 119   isb
 120   bx      lr
 121
 122 ArmSetTTBR0
 123   mcr     p15,0,r0,c2,c0,0
 124   isb
 125   bx      lr
 126
 127 ArmGetTTBR0BaseAddress
 128   mrc     p15,0,r0,c2,c0,0
 129   ldr     r1, = 0xFFFFC000
 130   and     r0, r0, r1
 131   isb
 132   bx      lr
 133
 134
 135 ArmSetDomainAccessControl
 136   mcr     p15,0,r0,c3,c0,0
 137   isb
 138   bx      lr
 139
 140 //
 141 //VOID
 142 //ArmUpdateTranslationTableEntry (
 143 //  IN VOID  *TranslationTableEntry  // R0
 144 //  IN VOID  *MVA                    // R1
 145 //  );
 146 ArmUpdateTranslationTableEntry
 147   mcr     p15,0,R0,c7,c14,1     ; DCCIMVAC Clean data cache by MVA
 148   dsb
 149   mcr     p15,0,R1,c8,c7,1      ; TLBIMVA TLB Invalidate MVA
 150   mcr     p15,0,R9,c7,c5,6      ; BPIALL Invalidate Branch predictor array. R9 == NoOp
 151   dsb
 152   isb
 153   bx      lr
 154
 155 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
 156   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
 157   mov     r3, sp            ; copy the stack pointer into a non-banked register
 158   mrs     r2, cpsr          ; read the cpsr
 159   bic     r2, r2, r0        ; clear mask in the cpsr
 160   and     r1, r1, r0        ; clear bits outside the mask in the input
 161   orr     r2, r2, r1        ; set field
 162   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
 163   isb
 164   mov     sp, r3            ; restore stack pointer
 165   ldmfd   sp!, {r4-r12, lr} ; restore registers
 166   bx      lr                ; return (hopefully thumb-safe!)
 167
 168 CPSRRead
 169   mrs     r0, cpsr
 170   bx      lr
 171
 172
 173 // UINT32
 174 // ReadCCSIDR (
 175 //   IN UINT32 CSSELR
 176 //   )
 177 ReadCCSIDR
 178   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
 179   isb
 180   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
 181   bx  lr
 182
 183
 184 // UINT32
 185 // ReadCLIDR (
 186 //   IN UINT32 CSSELR
 187 //   )
 188 ReadCLIDR
 189   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
 190   bx  lr
 191
 192 END