ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  Cp15IdCode
  17     EXPORT  Cp15CacheInfo
  18     EXPORT  ArmEnableInterrupts
  19     EXPORT  ArmDisableInterrupts
  20     EXPORT  ArmGetInterruptState
  21     EXPORT  ArmInvalidateTlb
  22     EXPORT  ArmSetTranslationTableBaseAddress
  23     EXPORT  ArmGetTranslationTableBaseAddress
  24     EXPORT  ArmSetDomainAccessControl
  25     EXPORT  CPSRMaskInsert
  26     EXPORT  CPSRRead
  27     EXPORT  ReadCCSIDR
  28     EXPORT  ReadCLIDR
  29
  30     AREA ArmLibSupport, CODE, READONLY
  31
  32 Cp15IdCode
  33   mrc     p15,0,R0,c0,c0,0
  34   bx      LR
  35
  36 Cp15CacheInfo
  37   mrc     p15,0,R0,c0,c0,1
  38   bx      LR
  39
  40 ArmEnableInterrupts
  41   CPSIE   i
  42         bx      LR
  43
  44 ArmDisableInterrupts
  45   CPSID   i
  46         bx      LR
  47
  48 ArmGetInterruptState
  49         mrs     R0,CPSR
  50         tst     R0,#0x80            ;Check if IRQ is enabled.
  51         moveq   R0,#1
  52         movne   R0,#0
  53         bx      LR
  54
  55 ArmInvalidateTlb
  56   mov     r0,#0
  57   mcr     p15,0,r0,c8,c7,0
  58   ISB
  59   bx      lr
  60
  61 ArmSetTranslationTableBaseAddress
  62   mcr     p15,0,r0,c2,c0,0
  63   ISB
  64   bx      lr
  65
  66 ArmGetTranslationTableBaseAddress
  67   mrc     p15,0,r0,c2,c0,0
  68   ISB
  69   bx      lr
  70
  71 ArmSetDomainAccessControl
  72   mcr     p15,0,r0,c3,c0,0
  73   ISB
  74   bx      lr
  75
  76 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
  77   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
  78   mov     r3, sp            ; copy the stack pointer into a non-banked register
  79   mrs     r2, cpsr          ; read the cpsr
  80   bic     r2, r2, r0        ; clear mask in the cpsr
  81   and     r1, r1, r0        ; clear bits outside the mask in the input
  82   orr     r2, r2, r1        ; set field
  83   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
  84   ISB
  85   mov     sp, r3            ; restore stack pointer
  86   ldmfd   sp!, {r4-r12, lr} ; restore registers
  87   bx      lr                ; return (hopefully thumb-safe!)
  88
  89 CPSRRead
  90   mrs     r0, cpsr
  91   bx      lr
  92
  93
  94 // UINT32
  95 // ReadCCSIDR (
  96 //   IN UINT32 CSSELR
  97 //   )
  98 ReadCCSIDR
  99   MCR p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
 100   ISB
 101   MRC p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
 102   BX  lr
 103
 104
 105 // UINT32
 106 // ReadCLIDR (
 107 //   IN UINT32 CSSELR
 108 //   )
 109 ReadCLIDR
 110   MRC p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
 111   END
 112
 113