ArmPkg/Library/ArmLib/ArmV7/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  Cp15IdCode
  17     EXPORT  Cp15CacheInfo
  18     EXPORT  ArmEnableInterrupts
  19     EXPORT  ArmDisableInterrupts
  20     EXPORT  ArmGetInterruptState
  21     EXPORT  ArmInvalidateTlb
  22     EXPORT  ArmSetTranslationTableBaseAddress
  23     EXPORT  ArmGetTranslationTableBaseAddress
  24     EXPORT  ArmSetDomainAccessControl
  25     EXPORT  CPSRMaskInsert
  26     EXPORT  CPSRRead
  27
  28     AREA ArmLibSupport, CODE, READONLY
  29
  30 Cp15IdCode
  31   DSB
  32   ISB
  33   mrc     p15,0,R0,c0,c0,0
  34   DSB
  35   ISB
  36   bx      LR
  37
  38 Cp15CacheInfo
  39   DSB
  40   ISB
  41   mrc     p15,0,R0,c0,c0,1
  42   DSB
  43   ISB
  44   bx      LR
  45
  46 ArmEnableInterrupts
  47   DSB
  48   ISB
  49         mrs     R0,CPSR
  50         bic     R0,R0,#0x80             ;Enable IRQ interrupts
  51         msr     CPSR_c,R0
  52   DSB
  53   ISB
  54         bx      LR
  55
  56 ArmDisableInterrupts
  57   DSB
  58   ISB
  59         mrs     R0,CPSR
  60         orr     R1,R0,#0x80             ;Disable IRQ interrupts
  61         msr     CPSR_c,R1
  62   tst     R0,#0x80
  63   moveq   R0,#1
  64   movne   R0,#0
  65   DSB
  66   ISB
  67         bx      LR
  68
  69 ArmGetInterruptState
  70   DSB
  71   ISB
  72         mrs     R0,CPSR
  73         tst     R0,#0x80            ;Check if IRQ is enabled.
  74         moveq   R0,#1
  75         movne   R0,#0
  76   DSB
  77   ISB
  78         bx      LR
  79
  80 ArmInvalidateTlb
  81   DSB
  82   ISB
  83   mov     r0,#0
  84   mcr     p15,0,r0,c8,c7,0
  85   DSB
  86   ISB
  87   bx      lr
  88
  89 ArmSetTranslationTableBaseAddress
  90   DSB
  91   ISB
  92   mcr     p15,0,r0,c2,c0,0
  93   DSB
  94   ISB
  95   bx      lr
  96
  97 ArmGetTranslationTableBaseAddress
  98   DSB
  99   ISB
 100   mrc     p15,0,r0,c2,c0,0
 101   DSB
 102   ISB
 103   bx      lr
 104
 105 ArmSetDomainAccessControl
 106   DSB
 107   ISB
 108   mcr     p15,0,r0,c3,c0,0
 109   DSB
 110   ISB
 111   bx      lr
 112
 113 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
 114   DSB
 115   ISB
 116   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
 117   mov     r3, sp            ; copy the stack pointer into a non-banked register
 118   mrs     r2, cpsr          ; read the cpsr
 119   bic     r2, r2, r0        ; clear mask in the cpsr
 120   and     r1, r1, r0        ; clear bits outside the mask in the input
 121   orr     r2, r2, r1        ; set field
 122   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
 123   mov     sp, r3            ; restore stack pointer
 124   ldmfd   sp!, {r4-r12, lr} ; restore registers
 125   DSB
 126   ISB
 127   bx      lr                ; return (hopefully thumb-safe!)
 128
 129 CPSRRead
 130   DSB
 131   ISB
 132   mrs     r0, cpsr
 133   DSB
 134   ISB
 135   bx      lr
 136
 137   END
 138
 139