ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18 .text
  19 .align 2
  20
  21 GCC_ASM_EXPORT(ArmIsMpCore)
  22 GCC_ASM_EXPORT(ArmEnableAsynchronousAbort)
  23 GCC_ASM_EXPORT(ArmDisableAsynchronousAbort)
  24 GCC_ASM_EXPORT(ArmEnableIrq)
  25 GCC_ASM_EXPORT(ArmDisableIrq)
  26 GCC_ASM_EXPORT(ArmEnableFiq)
  27 GCC_ASM_EXPORT(ArmDisableFiq)
  28 GCC_ASM_EXPORT(ArmEnableInterrupts)
  29 GCC_ASM_EXPORT(ArmDisableInterrupts)
  30 GCC_ASM_EXPORT(ReadCCSIDR)
  31 GCC_ASM_EXPORT(ReadCLIDR)
  32 GCC_ASM_EXPORT(ArmReadNsacr)
  33 GCC_ASM_EXPORT(ArmWriteNsacr)
  34
  35 #------------------------------------------------------------------------------
  36
  37 ASM_PFX(ArmIsMpCore):
  38   mrc     p15,0,R0,c0,c0,5
  39   // Get Multiprocessing extension (bit31) & U bit (bit30)
  40   and     R0, R0, #0xC0000000
  41   // if bit30 == 0 then the processor is part of a multiprocessor system)
  42   and     R0, R0, #0x80000000
  43   bx      LR
  44
  45 ASM_PFX(ArmEnableAsynchronousAbort):
  46   cpsie   a
  47   isb
  48   bx      LR
  49
  50 ASM_PFX(ArmDisableAsynchronousAbort):
  51   cpsid   a
  52   isb
  53   bx      LR
  54
  55 ASM_PFX(ArmEnableIrq):
  56   cpsie   i
  57   isb
  58   bx      LR
  59
  60 ASM_PFX(ArmDisableIrq):
  61   cpsid   i
  62   isb
  63   bx      LR
  64
  65 ASM_PFX(ArmEnableFiq):
  66   cpsie   f
  67   isb
  68   bx      LR
  69
  70 ASM_PFX(ArmDisableFiq):
  71   cpsid   f
  72   isb
  73   bx      LR
  74
  75 ASM_PFX(ArmEnableInterrupts):
  76   cpsie   if
  77   isb
  78   bx      LR
  79
  80 ASM_PFX(ArmDisableInterrupts):
  81   cpsid   if
  82   isb
  83   bx      LR
  84
  85 // UINT32
  86 // ReadCCSIDR (
  87 //   IN UINT32 CSSELR
  88 //   )
  89 ASM_PFX(ReadCCSIDR):
  90   mcr p15,2,r0,c0,c0,0   @ Write Cache Size Selection Register (CSSELR)
  91   isb
  92   mrc p15,1,r0,c0,c0,0   @ Read current CP15 Cache Size ID Register (CCSIDR)
  93   bx  lr
  94
  95 // UINT32
  96 // ReadCLIDR (
  97 //   IN UINT32 CSSELR
  98 //   )
  99 ASM_PFX(ReadCLIDR):
 100   mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
 101   bx  lr
 102
 103 ASM_PFX(ArmReadNsacr):
 104   mrc     p15, 0, r0, c1, c1, 2
 105   bx      lr
 106
 107 ASM_PFX(ArmWriteNsacr):
 108   mcr     p15, 0, r0, c1, c1, 2
 109   bx      lr
 110
 111 ASM_FUNCTION_REMOVE_IF_UNREFERENCED