ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17     EXPORT  ArmIsMpCore
  18     EXPORT  ArmEnableAsynchronousAbort
  19     EXPORT  ArmDisableAsynchronousAbort
  20     EXPORT  ArmEnableIrq
  21     EXPORT  ArmDisableIrq
  22     EXPORT  ArmEnableFiq
  23     EXPORT  ArmDisableFiq
  24     EXPORT  ArmEnableInterrupts
  25     EXPORT  ArmDisableInterrupts
  26     EXPORT  ReadCCSIDR
  27     EXPORT  ReadCLIDR
  28
  29     AREA ArmLibSupportV7, CODE, READONLY
  30
  31
  32 //------------------------------------------------------------------------------
  33
  34 ArmIsMpCore
  35   mrc     p15,0,R0,c0,c0,5
  36   // Get Multiprocessing extension (bit31) & U bit (bit30)
  37   and     R0, R0, #0xC0000000
  38   // if bit30 == 0 then the processor is part of a multiprocessor system)
  39   and     R0, R0, #0x80000000
  40   bx      LR
  41
  42 ArmEnableAsynchronousAbort
  43   cpsie   a
  44   isb
  45   bx      LR
  46
  47 ArmDisableAsynchronousAbort
  48   cpsid   a
  49   isb
  50   bx      LR
  51
  52 ArmEnableIrq
  53   cpsie   i
  54   isb
  55   bx      LR
  56
  57 ArmDisableIrq
  58   cpsid   i
  59   isb
  60   bx      LR
  61
  62 ArmEnableFiq
  63   cpsie   f
  64   isb
  65   bx      LR
  66
  67 ArmDisableFiq
  68   cpsid   f
  69   isb
  70   bx      LR
  71
  72 ArmEnableInterrupts
  73   cpsie   if
  74   isb
  75   bx      LR
  76
  77 ArmDisableInterrupts
  78   cpsid   if
  79   isb
  80   bx      LR
  81
  82 // UINT32
  83 // ReadCCSIDR (
  84 //   IN UINT32 CSSELR
  85 //   )
  86 ReadCCSIDR
  87   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  88   isb
  89   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
  90   bx  lr
  91
  92 // UINT32
  93 // ReadCLIDR (
  94 //   IN UINT32 CSSELR
  95 //   )
  96 ReadCLIDR
  97   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
  98   bx  lr
  99
 100 END