ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011-2013, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16
  17     EXPORT  ArmIsMpCore
  18     EXPORT  ArmEnableAsynchronousAbort
  19     EXPORT  ArmDisableAsynchronousAbort
  20     EXPORT  ArmEnableIrq
  21     EXPORT  ArmDisableIrq
  22     EXPORT  ArmEnableFiq
  23     EXPORT  ArmDisableFiq
  24     EXPORT  ArmEnableInterrupts
  25     EXPORT  ArmDisableInterrupts
  26     EXPORT  ReadCCSIDR
  27     EXPORT  ReadCLIDR
  28     EXPORT  ArmReadNsacr
  29     EXPORT  ArmWriteNsacr
  30
  31     AREA ArmLibSupportV7, CODE, READONLY
  32
  33
  34 //------------------------------------------------------------------------------
  35
  36 ArmIsMpCore
  37   mrc     p15,0,R0,c0,c0,5
  38   // Get Multiprocessing extension (bit31) & U bit (bit30)
  39   and     R0, R0, #0xC0000000
  40   // if bit30 == 0 then the processor is part of a multiprocessor system)
  41   and     R0, R0, #0x80000000
  42   bx      LR
  43
  44 ArmEnableAsynchronousAbort
  45   cpsie   a
  46   isb
  47   bx      LR
  48
  49 ArmDisableAsynchronousAbort
  50   cpsid   a
  51   isb
  52   bx      LR
  53
  54 ArmEnableIrq
  55   cpsie   i
  56   isb
  57   bx      LR
  58
  59 ArmDisableIrq
  60   cpsid   i
  61   isb
  62   bx      LR
  63
  64 ArmEnableFiq
  65   cpsie   f
  66   isb
  67   bx      LR
  68
  69 ArmDisableFiq
  70   cpsid   f
  71   isb
  72   bx      LR
  73
  74 ArmEnableInterrupts
  75   cpsie   if
  76   isb
  77   bx      LR
  78
  79 ArmDisableInterrupts
  80   cpsid   if
  81   isb
  82   bx      LR
  83
  84 // UINT32
  85 // ReadCCSIDR (
  86 //   IN UINT32 CSSELR
  87 //   )
  88 ReadCCSIDR
  89   mcr p15,2,r0,c0,c0,0   ; Write Cache Size Selection Register (CSSELR)
  90   isb
  91   mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
  92   bx  lr
  93
  94 // UINT32
  95 // ReadCLIDR (
  96 //   IN UINT32 CSSELR
  97 //   )
  98 ReadCLIDR
  99   mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
 100   bx  lr
 101
 102 ArmReadNsacr
 103   mrc     p15, 0, r0, c1, c1, 2
 104   bx      lr
 105
 106 ArmWriteNsacr
 107   mcr     p15, 0, r0, c1, c1, 2
 108   bx      lr
 109
 110   END